1 | ; ---------------------------------------------------------------
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2 | ; Copyright 2010, Adrien Destugues <pulkomandy@pulkomandy.ath.cx>
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3 | ; Distributed under the terms of the MIT Licence
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4 |
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5 | ; Firmware for µSerial expansion board
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6 |
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7 | ; Vectors
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8 | ; reset
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9 | ; int0
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10 | RJMP cpc_write
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11 | ; int1
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12 | RJMP cpc_read
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13 | ; ...
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14 |
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15 | ; Interrupt vectors for external INT pins (read and write).
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16 | ; we have to react very quick.
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17 | ; A read operation for the CPC lasts 3 clock cycles at 4MHz, that's 15
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18 | ; AVR cycles. But the interrupt latency is as follow :
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19 | ; Lowlevel detection ; 2 cycles
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20 | ; End of running instruction ; up to 2 cycles
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21 | ; Save PC ; 4 cycles
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22 | ;Vector RJMP ; 2 cycles
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23 | ; TOTAL => 10 cycles
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24 |
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25 | ; --- READ INTERRUPT ---
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26 | cpc_read
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27 | ; That means we only have 5 cycles left to output the value on the BUS!
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28 | ; We have no time to do anything, so we assume that X is already pointing at
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29 | ; the right place and we just OUT it to the data port. We have no time for
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30 | ; PUSHing and loading it, anyway.
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31 |
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32 | ; Note you can read from either port and get the same result. Two reasons to
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33 | ; that : you can already access all the registers and part of the SRAM,
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34 | ; and there's no time to do something more clever.
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35 |
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36 | ; There is no time to push/pop regs, so we just use X as is. R27 is part of X.
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37 |
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38 | ; We assume X (R26:R27) points to the current reg
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39 | ; So we can load it and react fast enough to the interrupt
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40 | LDI R0,ALL_OUT ; 1 ; peut être économisé si on sacrifie un reg
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41 | OUT DATADIR,R0 ; 1
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42 | LD R27,(X) ; 2 cycles ; peut être économisé si un reg. contient
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43 | ; déjà la valeur à envoyer
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44 | ; (mais qui l'update ?)
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45 | OUT DATA, R27 ; 1 cycle
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46 |
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47 | ; Here data is sent, the CPC read operation is handled.
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48 | ; We now wait for the end of the read cycle.
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49 | ; This is not the end of the time-constrained nightmare, however :
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50 | ; In the worst case, the CPC can do another OUT or IN right after,
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51 | ; so we don't have an infinite number of cycles to handle the interrupt.
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52 | ; it is much more relaxed, as we have 12 CPC cycles = 60 AVR cycles free.
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53 |
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54 | ; Restore R27
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55 | LD R27,curregbak
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56 | LD R27,(X)
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57 |
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58 | ; release the bus
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59 | LDI R0,ALL_IN
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60 | OUT DATADIR, R0
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61 |
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62 | ; Restore R27 to selected reg. (we erased it to do the OUT)
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63 | RETI
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64 |
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65 | ; --- WRITE INTERRUPT ---
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66 | cpc_write
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67 | ; The timing is a bit less constraining here.
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68 | PUSH R0
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69 | IN R0,DATA
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70 | ; we also need to know A0 state...
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71 | SBIS CTRL,A0
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72 | ; This was actually a reg select operation!
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73 | ; Jump to the proper code
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74 | RJMP regSel
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75 | ; We have read the CPC data. End of the heavy-constraint area
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76 |
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77 | ; Register write
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78 | ST X,R0 ; Normal register write
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79 | RJMP intEnd
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80 |
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81 | regSel
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82 | LD R27,curregbak
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83 | ST (X),R0
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84 | MOV R27,R0
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85 |
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86 | POP R0
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87 | RETI
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88 |
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89 |
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90 | ; --- RESET VECTOR ---
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91 | ; Here we perform the hardware initialization.
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92 | ; At a bare minimum :
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93 | ; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself
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