[3587f7f] | 1 | /* Name: usbdrvasm12.inc
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| 2 | * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
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| 3 | * Author: Christian Starkjohann
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| 4 | * Creation Date: 2004-12-29
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| 5 | * Tabsize: 4
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| 6 | * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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| 7 | * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
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| 8 | * This Revision: $Id: usbdrvasm12.inc 740 2009-04-13 18:23:31Z cs $
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| 9 | */
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| 10 |
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| 11 | /* Do not link this file! Link usbdrvasm.S instead, which includes the
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| 12 | * appropriate implementation!
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| 13 | */
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| 14 |
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| 15 | /*
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| 16 | General Description:
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| 17 | This file is the 12 MHz version of the asssembler part of the USB driver. It
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| 18 | requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC
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| 19 | oscillator).
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| 20 |
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| 21 | See usbdrv.h for a description of the entire driver.
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| 22 |
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| 23 | Since almost all of this code is timing critical, don't change unless you
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| 24 | really know what you are doing! Many parts require not only a maximum number
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| 25 | of CPU cycles, but even an exact number of cycles!
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| 26 |
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| 27 |
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| 28 | Timing constraints according to spec (in bit times):
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| 29 | timing subject min max CPUcycles
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| 30 | ---------------------------------------------------------------------------
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| 31 | EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
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| 32 | EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
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| 33 | DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
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| 34 | */
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| 35 |
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| 36 | ;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
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| 37 | ;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
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| 38 | ;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable
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| 39 | ;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes
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| 40 | ;Numbers in brackets are maximum cycles since SOF.
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| 41 | USB_INTR_VECTOR:
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| 42 | ;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt
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| 43 | push YL ;2 [35] push only what is necessary to sync with edge ASAP
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| 44 | in YL, SREG ;1 [37]
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| 45 | push YL ;2 [39]
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| 46 | ;----------------------------------------------------------------------------
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| 47 | ; Synchronize with sync pattern:
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| 48 | ;----------------------------------------------------------------------------
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| 49 | ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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| 50 | ;sync up with J to K edge during sync pattern -- use fastest possible loops
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| 51 | ;The first part waits at most 1 bit long since we must be in sync pattern.
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| 52 | ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
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| 53 | ;waitForJ, ensure that this prerequisite is met.
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| 54 | waitForJ:
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| 55 | inc YL
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| 56 | sbis USBIN, USBMINUS
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| 57 | brne waitForJ ; just make sure we have ANY timeout
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| 58 | waitForK:
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| 59 | ;The following code results in a sampling window of 1/4 bit which meets the spec.
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| 60 | sbis USBIN, USBMINUS
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| 61 | rjmp foundK
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| 62 | sbis USBIN, USBMINUS
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| 63 | rjmp foundK
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| 64 | sbis USBIN, USBMINUS
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| 65 | rjmp foundK
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| 66 | sbis USBIN, USBMINUS
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| 67 | rjmp foundK
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| 68 | sbis USBIN, USBMINUS
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| 69 | rjmp foundK
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| 70 | #if USB_COUNT_SOF
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| 71 | lds YL, usbSofCount
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| 72 | inc YL
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| 73 | sts usbSofCount, YL
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| 74 | #endif /* USB_COUNT_SOF */
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| 75 | #ifdef USB_SOF_HOOK
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| 76 | USB_SOF_HOOK
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| 77 | #endif
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| 78 | rjmp sofError
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| 79 | foundK:
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| 80 | ;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
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| 81 | ;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
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| 82 | ;are cycles from center of first sync (double K) bit after the instruction
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| 83 | push YH ;2 [2]
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| 84 | lds YL, usbInputBufOffset;2 [4]
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| 85 | clr YH ;1 [5]
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| 86 | subi YL, lo8(-(usbRxBuf));1 [6]
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| 87 | sbci YH, hi8(-(usbRxBuf));1 [7]
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| 88 |
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| 89 | sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early]
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| 90 | rjmp haveTwoBitsK ;2 [10]
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| 91 | pop YH ;2 [11] undo the push from before
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| 92 | rjmp waitForK ;2 [13] this was not the end of sync, retry
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| 93 | haveTwoBitsK:
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| 94 | ;----------------------------------------------------------------------------
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| 95 | ; push more registers and initialize values while we sample the first bits:
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| 96 | ;----------------------------------------------------------------------------
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| 97 | push shift ;2 [16]
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| 98 | push x1 ;2 [12]
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| 99 | push x2 ;2 [14]
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| 100 |
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| 101 | in x1, USBIN ;1 [17] <-- sample bit 0
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| 102 | ldi shift, 0xff ;1 [18]
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| 103 | bst x1, USBMINUS ;1 [19]
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| 104 | bld shift, 0 ;1 [20]
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| 105 | push x3 ;2 [22]
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| 106 | push cnt ;2 [24]
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| 107 |
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| 108 | in x2, USBIN ;1 [25] <-- sample bit 1
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| 109 | ser x3 ;1 [26] [inserted init instruction]
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| 110 | eor x1, x2 ;1 [27]
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| 111 | bst x1, USBMINUS ;1 [28]
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| 112 | bld shift, 1 ;1 [29]
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| 113 | ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction]
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| 114 | rjmp rxbit2 ;2 [32]
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| 115 |
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| 116 | ;----------------------------------------------------------------------------
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| 117 | ; Receiver loop (numbers in brackets are cycles within byte after instr)
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| 118 | ;----------------------------------------------------------------------------
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| 119 |
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| 120 | unstuff0: ;1 (branch taken)
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| 121 | andi x3, ~0x01 ;1 [15]
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| 122 | mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit
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| 123 | in x2, USBIN ;1 [17] <-- sample bit 1 again
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| 124 | ori shift, 0x01 ;1 [18]
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| 125 | rjmp didUnstuff0 ;2 [20]
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| 126 |
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| 127 | unstuff1: ;1 (branch taken)
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| 128 | mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit
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| 129 | andi x3, ~0x02 ;1 [22]
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| 130 | ori shift, 0x02 ;1 [23]
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| 131 | nop ;1 [24]
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| 132 | in x1, USBIN ;1 [25] <-- sample bit 2 again
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| 133 | rjmp didUnstuff1 ;2 [27]
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| 134 |
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| 135 | unstuff2: ;1 (branch taken)
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| 136 | andi x3, ~0x04 ;1 [29]
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| 137 | ori shift, 0x04 ;1 [30]
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| 138 | mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit
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| 139 | nop ;1 [32]
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| 140 | in x2, USBIN ;1 [33] <-- sample bit 3
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| 141 | rjmp didUnstuff2 ;2 [35]
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| 142 |
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| 143 | unstuff3: ;1 (branch taken)
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| 144 | in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late]
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| 145 | andi x3, ~0x08 ;1 [35]
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| 146 | ori shift, 0x08 ;1 [36]
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| 147 | rjmp didUnstuff3 ;2 [38]
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| 148 |
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| 149 | unstuff4: ;1 (branch taken)
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| 150 | andi x3, ~0x10 ;1 [40]
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| 151 | in x1, USBIN ;1 [41] <-- sample stuffed bit 4
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| 152 | ori shift, 0x10 ;1 [42]
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| 153 | rjmp didUnstuff4 ;2 [44]
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| 154 |
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| 155 | unstuff5: ;1 (branch taken)
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| 156 | andi x3, ~0x20 ;1 [48]
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| 157 | in x2, USBIN ;1 [49] <-- sample stuffed bit 5
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| 158 | ori shift, 0x20 ;1 [50]
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| 159 | rjmp didUnstuff5 ;2 [52]
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| 160 |
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| 161 | unstuff6: ;1 (branch taken)
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| 162 | andi x3, ~0x40 ;1 [56]
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| 163 | in x1, USBIN ;1 [57] <-- sample stuffed bit 6
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| 164 | ori shift, 0x40 ;1 [58]
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| 165 | rjmp didUnstuff6 ;2 [60]
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| 166 |
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| 167 | ; extra jobs done during bit interval:
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| 168 | ; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs]
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| 169 | ; bit 1: se0 check
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| 170 | ; bit 2: overflow check
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| 171 | ; bit 3: recovery from delay [bit 0 tasks took too long]
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| 172 | ; bit 4: none
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| 173 | ; bit 5: none
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| 174 | ; bit 6: none
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| 175 | ; bit 7: jump, eor
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| 176 | rxLoop:
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| 177 | eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others
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| 178 | in x1, USBIN ;1 [1] <-- sample bit 0
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| 179 | st y+, x3 ;2 [3] store data
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| 180 | ser x3 ;1 [4]
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| 181 | nop ;1 [5]
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| 182 | eor x2, x1 ;1 [6]
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| 183 | bst x2, USBMINUS;1 [7]
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| 184 | bld shift, 0 ;1 [8]
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| 185 | in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed)
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| 186 | andi x2, USBMASK ;1 [10]
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| 187 | breq se0 ;1 [11] SE0 check for bit 1
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| 188 | andi shift, 0xf9 ;1 [12]
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| 189 | didUnstuff0:
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| 190 | breq unstuff0 ;1 [13]
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| 191 | eor x1, x2 ;1 [14]
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| 192 | bst x1, USBMINUS;1 [15]
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| 193 | bld shift, 1 ;1 [16]
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| 194 | rxbit2:
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| 195 | in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed)
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| 196 | andi shift, 0xf3 ;1 [18]
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| 197 | breq unstuff1 ;1 [19] do remaining work for bit 1
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| 198 | didUnstuff1:
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| 199 | subi cnt, 1 ;1 [20]
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| 200 | brcs overflow ;1 [21] loop control
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| 201 | eor x2, x1 ;1 [22]
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| 202 | bst x2, USBMINUS;1 [23]
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| 203 | bld shift, 2 ;1 [24]
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| 204 | in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed)
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| 205 | andi shift, 0xe7 ;1 [26]
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| 206 | breq unstuff2 ;1 [27]
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| 207 | didUnstuff2:
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| 208 | eor x1, x2 ;1 [28]
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| 209 | bst x1, USBMINUS;1 [29]
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| 210 | bld shift, 3 ;1 [30]
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| 211 | didUnstuff3:
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| 212 | andi shift, 0xcf ;1 [31]
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| 213 | breq unstuff3 ;1 [32]
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| 214 | in x1, USBIN ;1 [33] <-- sample bit 4
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| 215 | eor x2, x1 ;1 [34]
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| 216 | bst x2, USBMINUS;1 [35]
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| 217 | bld shift, 4 ;1 [36]
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| 218 | didUnstuff4:
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| 219 | andi shift, 0x9f ;1 [37]
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| 220 | breq unstuff4 ;1 [38]
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| 221 | nop2 ;2 [40]
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| 222 | in x2, USBIN ;1 [41] <-- sample bit 5
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| 223 | eor x1, x2 ;1 [42]
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| 224 | bst x1, USBMINUS;1 [43]
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| 225 | bld shift, 5 ;1 [44]
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| 226 | didUnstuff5:
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| 227 | andi shift, 0x3f ;1 [45]
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| 228 | breq unstuff5 ;1 [46]
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| 229 | nop2 ;2 [48]
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| 230 | in x1, USBIN ;1 [49] <-- sample bit 6
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| 231 | eor x2, x1 ;1 [50]
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| 232 | bst x2, USBMINUS;1 [51]
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| 233 | bld shift, 6 ;1 [52]
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| 234 | didUnstuff6:
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| 235 | cpi shift, 0x02 ;1 [53]
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| 236 | brlo unstuff6 ;1 [54]
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| 237 | nop2 ;2 [56]
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| 238 | in x2, USBIN ;1 [57] <-- sample bit 7
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| 239 | eor x1, x2 ;1 [58]
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| 240 | bst x1, USBMINUS;1 [59]
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| 241 | bld shift, 7 ;1 [60]
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| 242 | didUnstuff7:
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| 243 | cpi shift, 0x04 ;1 [61]
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| 244 | brsh rxLoop ;2 [63] loop control
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| 245 | unstuff7:
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| 246 | andi x3, ~0x80 ;1 [63]
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| 247 | ori shift, 0x80 ;1 [64]
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| 248 | in x2, USBIN ;1 [65] <-- sample stuffed bit 7
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| 249 | nop ;1 [66]
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| 250 | rjmp didUnstuff7 ;2 [68]
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| 251 |
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| 252 | macro POP_STANDARD ; 12 cycles
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| 253 | pop cnt
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| 254 | pop x3
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| 255 | pop x2
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| 256 | pop x1
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| 257 | pop shift
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| 258 | pop YH
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| 259 | endm
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| 260 | macro POP_RETI ; 5 cycles
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| 261 | pop YL
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| 262 | out SREG, YL
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| 263 | pop YL
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| 264 | endm
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| 265 |
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| 266 | #include "asmcommon.inc"
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| 267 |
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| 268 | ;----------------------------------------------------------------------------
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| 269 | ; Transmitting data
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| 270 | ;----------------------------------------------------------------------------
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| 271 |
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| 272 | txByteLoop:
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| 273 | txBitloop:
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| 274 | stuffN1Delay: ; [03]
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| 275 | ror shift ;[-5] [11] [59]
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| 276 | brcc doExorN1 ;[-4] [60]
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| 277 | subi x4, 1 ;[-3]
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| 278 | brne commonN1 ;[-2]
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| 279 | lsl shift ;[-1] compensate ror after rjmp stuffDelay
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| 280 | nop ;[00] stuffing consists of just waiting 8 cycles
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| 281 | rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear
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| 282 |
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| 283 | sendNakAndReti: ;0 [-19] 19 cycles until SOP
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| 284 | ldi x3, USBPID_NAK ;1 [-18]
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| 285 | rjmp usbSendX3 ;2 [-16]
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| 286 | sendAckAndReti: ;0 [-19] 19 cycles until SOP
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| 287 | ldi x3, USBPID_ACK ;1 [-18]
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| 288 | rjmp usbSendX3 ;2 [-16]
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| 289 | sendCntAndReti: ;0 [-17] 17 cycles until SOP
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| 290 | mov x3, cnt ;1 [-16]
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| 291 | usbSendX3: ;0 [-16]
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| 292 | ldi YL, 20 ;1 [-15] 'x3' is R20
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| 293 | ldi YH, 0 ;1 [-14]
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| 294 | ldi cnt, 2 ;1 [-13]
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| 295 | ; rjmp usbSendAndReti fallthrough
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| 296 |
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| 297 | ; USB spec says:
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| 298 | ; idle = J
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| 299 | ; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
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| 300 | ; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
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| 301 | ; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
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| 302 |
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| 303 | ;usbSend:
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| 304 | ;pointer to data in 'Y'
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| 305 | ;number of bytes in 'cnt' -- including sync byte
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| 306 | ;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt]
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| 307 | ;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction)
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| 308 | usbSendAndReti:
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| 309 | in x2, USBDDR ;[-12] 12 cycles until SOP
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| 310 | ori x2, USBMASK ;[-11]
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| 311 | sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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| 312 | out USBDDR, x2 ;[-8] <--- acquire bus
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| 313 | in x1, USBOUT ;[-7] port mirror for tx loop
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| 314 | ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror)
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| 315 | ldi x2, USBMASK ;[-5]
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| 316 | push x4 ;[-4]
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| 317 | doExorN1:
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| 318 | eor x1, x2 ;[-2] [06] [62]
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| 319 | ldi x4, 6 ;[-1] [07] [63]
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| 320 | commonN1:
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| 321 | stuffN2Delay:
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| 322 | out USBOUT, x1 ;[00] [08] [64] <--- set bit
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| 323 | ror shift ;[01]
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| 324 | brcc doExorN2 ;[02]
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| 325 | subi x4, 1 ;[03]
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| 326 | brne commonN2 ;[04]
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| 327 | lsl shift ;[05] compensate ror after rjmp stuffDelay
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| 328 | rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear
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| 329 | doExorN2:
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| 330 | eor x1, x2 ;[04] [12]
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| 331 | ldi x4, 6 ;[05] [13]
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| 332 | commonN2:
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| 333 | nop ;[06] [14]
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| 334 | subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1
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| 335 | out USBOUT, x1 ;[08] [16] <--- set bit
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| 336 | brcs txBitloop ;[09] [25] [41]
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| 337 |
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| 338 | stuff6Delay:
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| 339 | ror shift ;[42] [50]
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| 340 | brcc doExor6 ;[43]
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| 341 | subi x4, 1 ;[44]
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| 342 | brne common6 ;[45]
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| 343 | lsl shift ;[46] compensate ror after rjmp stuffDelay
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| 344 | nop ;[47] stuffing consists of just waiting 8 cycles
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| 345 | rjmp stuff6Delay ;[48] after ror, C bit is reliably clear
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| 346 | doExor6:
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| 347 | eor x1, x2 ;[45] [53]
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| 348 | ldi x4, 6 ;[46]
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| 349 | common6:
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| 350 | stuff7Delay:
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| 351 | ror shift ;[47] [55]
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| 352 | out USBOUT, x1 ;[48] <--- set bit
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| 353 | brcc doExor7 ;[49]
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| 354 | subi x4, 1 ;[50]
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| 355 | brne common7 ;[51]
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| 356 | lsl shift ;[52] compensate ror after rjmp stuffDelay
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| 357 | rjmp stuff7Delay ;[53] after ror, C bit is reliably clear
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| 358 | doExor7:
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| 359 | eor x1, x2 ;[51] [59]
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| 360 | ldi x4, 6 ;[52]
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| 361 | common7:
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| 362 | ld shift, y+ ;[53]
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| 363 | tst cnt ;[55]
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| 364 | out USBOUT, x1 ;[56] <--- set bit
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| 365 | brne txByteLoop ;[57]
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| 366 |
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| 367 | ;make SE0:
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| 368 | cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles]
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| 369 | lds x2, usbNewDeviceAddr;[59]
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| 370 | lsl x2 ;[61] we compare with left shifted address
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| 371 | subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3
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| 372 | sbci YH, 0 ;[63]
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| 373 | out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
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| 374 | ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
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| 375 | ;set address only after data packet was sent, not after handshake
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| 376 | breq skipAddrAssign ;[01]
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| 377 | sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
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| 378 | skipAddrAssign:
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| 379 | ;end of usbDeviceAddress transfer
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| 380 | ldi x2, 1<<USB_INTR_PENDING_BIT;[03] int0 occurred during TX -- clear pending flag
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| 381 | USB_STORE_PENDING(x2) ;[04]
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| 382 | ori x1, USBIDLE ;[05]
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| 383 | in x2, USBDDR ;[06]
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| 384 | cbr x2, USBMASK ;[07] set both pins to input
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| 385 | mov x3, x1 ;[08]
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| 386 | cbr x3, USBMASK ;[09] configure no pullup on both pins
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| 387 | pop x4 ;[10]
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| 388 | nop2 ;[12]
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| 389 | nop2 ;[14]
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| 390 | out USBOUT, x1 ;[16] <-- out J (idle) -- end of SE0 (EOP signal)
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| 391 | out USBDDR, x2 ;[17] <-- release bus now
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| 392 | out USBOUT, x3 ;[18] <-- ensure no pull-up resistors are active
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| 393 | rjmp doReturn
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