[3587f7f] | 1 | /* Name: usbdrvasm16.inc
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| 2 | * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
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| 3 | * Author: Christian Starkjohann
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| 4 | * Creation Date: 2007-06-15
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| 5 | * Tabsize: 4
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| 6 | * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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| 7 | * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
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| 8 | * Revision: $Id: usbdrvasm16.inc 760 2009-08-09 18:59:43Z cs $
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| 9 | */
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| 10 |
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| 11 | /* Do not link this file! Link usbdrvasm.S instead, which includes the
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| 12 | * appropriate implementation!
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| 13 | */
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| 14 |
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| 15 | /*
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| 16 | General Description:
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| 17 | This file is the 16 MHz version of the asssembler part of the USB driver. It
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| 18 | requires a 16 MHz crystal (not a ceramic resonator and not a calibrated RC
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| 19 | oscillator).
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| 20 |
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| 21 | See usbdrv.h for a description of the entire driver.
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| 22 |
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| 23 | Since almost all of this code is timing critical, don't change unless you
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| 24 | really know what you are doing! Many parts require not only a maximum number
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| 25 | of CPU cycles, but even an exact number of cycles!
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| 26 | */
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| 27 |
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| 28 | ;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
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| 29 | ;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte
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| 30 | ; Numbers in brackets are clocks counted from center of last sync bit
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| 31 | ; when instruction starts
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| 32 |
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| 33 | USB_INTR_VECTOR:
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| 34 | ;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
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| 35 | push YL ;[-25] push only what is necessary to sync with edge ASAP
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| 36 | in YL, SREG ;[-23]
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| 37 | push YL ;[-22]
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| 38 | push YH ;[-20]
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| 39 | ;----------------------------------------------------------------------------
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| 40 | ; Synchronize with sync pattern:
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| 41 | ;----------------------------------------------------------------------------
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| 42 | ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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| 43 | ;sync up with J to K edge during sync pattern -- use fastest possible loops
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| 44 | ;The first part waits at most 1 bit long since we must be in sync pattern.
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| 45 | ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
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| 46 | ;waitForJ, ensure that this prerequisite is met.
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| 47 | waitForJ:
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| 48 | inc YL
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| 49 | sbis USBIN, USBMINUS
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| 50 | brne waitForJ ; just make sure we have ANY timeout
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| 51 | waitForK:
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| 52 | ;The following code results in a sampling window of < 1/4 bit which meets the spec.
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| 53 | sbis USBIN, USBMINUS ;[-15]
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| 54 | rjmp foundK ;[-14]
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| 55 | sbis USBIN, USBMINUS
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| 56 | rjmp foundK
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| 57 | sbis USBIN, USBMINUS
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| 58 | rjmp foundK
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| 59 | sbis USBIN, USBMINUS
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| 60 | rjmp foundK
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| 61 | sbis USBIN, USBMINUS
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| 62 | rjmp foundK
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| 63 | sbis USBIN, USBMINUS
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| 64 | rjmp foundK
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| 65 | #if USB_COUNT_SOF
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| 66 | lds YL, usbSofCount
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| 67 | inc YL
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| 68 | sts usbSofCount, YL
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| 69 | #endif /* USB_COUNT_SOF */
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| 70 | #ifdef USB_SOF_HOOK
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| 71 | USB_SOF_HOOK
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| 72 | #endif
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| 73 | rjmp sofError
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| 74 | foundK: ;[-12]
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| 75 | ;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
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| 76 | ;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
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| 77 | ;are cycles from center of first sync (double K) bit after the instruction
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| 78 | push bitcnt ;[-12]
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| 79 | ; [---] ;[-11]
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| 80 | lds YL, usbInputBufOffset;[-10]
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| 81 | ; [---] ;[-9]
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| 82 | clr YH ;[-8]
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| 83 | subi YL, lo8(-(usbRxBuf));[-7] [rx loop init]
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| 84 | sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init]
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| 85 | push shift ;[-5]
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| 86 | ; [---] ;[-4]
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| 87 | ldi bitcnt, 0x55 ;[-3] [rx loop init]
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| 88 | sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
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| 89 | rjmp haveTwoBitsK ;[-1]
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| 90 | pop shift ;[0] undo the push from before
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| 91 | pop bitcnt ;[2] undo the push from before
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| 92 | rjmp waitForK ;[4] this was not the end of sync, retry
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| 93 | ; The entire loop from waitForK until rjmp waitForK above must not exceed two
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| 94 | ; bit times (= 21 cycles).
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| 95 |
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| 96 | ;----------------------------------------------------------------------------
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| 97 | ; push more registers and initialize values while we sample the first bits:
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| 98 | ;----------------------------------------------------------------------------
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| 99 | haveTwoBitsK:
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| 100 | push x1 ;[1]
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| 101 | push x2 ;[3]
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| 102 | push x3 ;[5]
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| 103 | ldi shift, 0 ;[7]
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| 104 | ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that
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| 105 | push x4 ;[9] == leap
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| 106 |
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| 107 | in x1, USBIN ;[11] <-- sample bit 0
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| 108 | andi x1, USBMASK ;[12]
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| 109 | bst x1, USBMINUS ;[13]
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| 110 | bld shift, 7 ;[14]
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| 111 | push cnt ;[15]
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| 112 | ldi leap, 0 ;[17] [rx loop init]
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| 113 | ldi cnt, USB_BUFSIZE;[18] [rx loop init]
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| 114 | rjmp rxbit1 ;[19] arrives at [21]
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| 115 |
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| 116 | ;----------------------------------------------------------------------------
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| 117 | ; Receiver loop (numbers in brackets are cycles within byte after instr)
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| 118 | ;----------------------------------------------------------------------------
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| 119 |
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| 120 | ; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap"
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| 121 | ; accordingly to approximate this value in the long run.
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| 122 |
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| 123 | unstuff6:
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| 124 | andi x2, USBMASK ;[03]
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| 125 | ori x3, 1<<6 ;[04] will not be shifted any more
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| 126 | andi shift, ~0x80;[05]
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| 127 | mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6
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| 128 | subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3
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| 129 | rjmp didUnstuff6 ;[08]
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| 130 |
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| 131 | unstuff7:
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| 132 | ori x3, 1<<7 ;[09] will not be shifted any more
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| 133 | in x2, USBIN ;[00] [10] re-sample bit 7
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| 134 | andi x2, USBMASK ;[01]
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| 135 | andi shift, ~0x80;[02]
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| 136 | subi leap, 2 ;[03] total duration = 10 bits -> add 1/3
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| 137 | rjmp didUnstuff7 ;[04]
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| 138 |
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| 139 | unstuffEven:
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| 140 | ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0
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| 141 | in x1, USBIN ;[00] [10]
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| 142 | andi shift, ~0x80;[01]
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| 143 | andi x1, USBMASK ;[02]
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| 144 | breq se0 ;[03]
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| 145 | subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3
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| 146 | nop2 ;[05]
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| 147 | rjmp didUnstuffE ;[06]
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| 148 |
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| 149 | unstuffOdd:
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| 150 | ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1
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| 151 | in x2, USBIN ;[00] [10]
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| 152 | andi shift, ~0x80;[01]
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| 153 | andi x2, USBMASK ;[02]
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| 154 | breq se0 ;[03]
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| 155 | subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3
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| 156 | nop2 ;[05]
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| 157 | rjmp didUnstuffO ;[06]
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| 158 |
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| 159 | rxByteLoop:
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| 160 | andi x1, USBMASK ;[03]
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| 161 | eor x2, x1 ;[04]
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| 162 | subi leap, 1 ;[05]
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| 163 | brpl skipLeap ;[06]
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| 164 | subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte
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| 165 | nop ;1
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| 166 | skipLeap:
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| 167 | subi x2, 1 ;[08]
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| 168 | ror shift ;[09]
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| 169 | didUnstuff6:
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| 170 | cpi shift, 0xfc ;[10]
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| 171 | in x2, USBIN ;[00] [11] <-- sample bit 7
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| 172 | brcc unstuff6 ;[01]
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| 173 | andi x2, USBMASK ;[02]
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| 174 | eor x1, x2 ;[03]
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| 175 | subi x1, 1 ;[04]
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| 176 | ror shift ;[05]
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| 177 | didUnstuff7:
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| 178 | cpi shift, 0xfc ;[06]
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| 179 | brcc unstuff7 ;[07]
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| 180 | eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others
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| 181 | st y+, x3 ;[09] store data
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| 182 | rxBitLoop:
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| 183 | in x1, USBIN ;[00] [11] <-- sample bit 0/2/4
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| 184 | andi x1, USBMASK ;[01]
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| 185 | eor x2, x1 ;[02]
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| 186 | andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7
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| 187 | subi x2, 1 ;[04]
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| 188 | ror shift ;[05]
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| 189 | cpi shift, 0xfc ;[06]
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| 190 | brcc unstuffEven ;[07]
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| 191 | didUnstuffE:
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| 192 | lsr x3 ;[08]
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| 193 | lsr x3 ;[09]
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| 194 | rxbit1:
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| 195 | in x2, USBIN ;[00] [10] <-- sample bit 1/3/5
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| 196 | andi x2, USBMASK ;[01]
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| 197 | breq se0 ;[02]
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| 198 | eor x1, x2 ;[03]
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| 199 | subi x1, 1 ;[04]
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| 200 | ror shift ;[05]
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| 201 | cpi shift, 0xfc ;[06]
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| 202 | brcc unstuffOdd ;[07]
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| 203 | didUnstuffO:
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| 204 | subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3
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| 205 | brcs rxBitLoop ;[09]
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| 206 |
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| 207 | subi cnt, 1 ;[10]
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| 208 | in x1, USBIN ;[00] [11] <-- sample bit 6
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| 209 | brcc rxByteLoop ;[01]
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| 210 | rjmp overflow
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| 211 |
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| 212 | macro POP_STANDARD ; 14 cycles
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| 213 | pop cnt
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| 214 | pop x4
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| 215 | pop x3
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| 216 | pop x2
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| 217 | pop x1
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| 218 | pop shift
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| 219 | pop bitcnt
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| 220 | endm
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| 221 | macro POP_RETI ; 7 cycles
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| 222 | pop YH
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| 223 | pop YL
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| 224 | out SREG, YL
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| 225 | pop YL
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| 226 | endm
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| 227 |
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| 228 | #include "asmcommon.inc"
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| 229 |
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| 230 | ; USB spec says:
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| 231 | ; idle = J
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| 232 | ; J = (D+ = 0), (D- = 1)
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| 233 | ; K = (D+ = 1), (D- = 0)
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| 234 | ; Spec allows 7.5 bit times from EOP to SOP for replies
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| 235 |
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| 236 | bitstuffN:
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| 237 | eor x1, x4 ;[5]
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| 238 | ldi x2, 0 ;[6]
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| 239 | nop2 ;[7]
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| 240 | nop ;[9]
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| 241 | out USBOUT, x1 ;[10] <-- out
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| 242 | rjmp didStuffN ;[0]
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| 243 |
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| 244 | bitstuff6:
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| 245 | eor x1, x4 ;[5]
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| 246 | ldi x2, 0 ;[6] Carry is zero due to brcc
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| 247 | rol shift ;[7] compensate for ror shift at branch destination
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| 248 | rjmp didStuff6 ;[8]
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| 249 |
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| 250 | bitstuff7:
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| 251 | ldi x2, 0 ;[2] Carry is zero due to brcc
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| 252 | rjmp didStuff7 ;[3]
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| 253 |
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| 254 |
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| 255 | sendNakAndReti:
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| 256 | ldi x3, USBPID_NAK ;[-18]
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| 257 | rjmp sendX3AndReti ;[-17]
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| 258 | sendAckAndReti:
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| 259 | ldi cnt, USBPID_ACK ;[-17]
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| 260 | sendCntAndReti:
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| 261 | mov x3, cnt ;[-16]
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| 262 | sendX3AndReti:
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| 263 | ldi YL, 20 ;[-15] x3==r20 address is 20
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| 264 | ldi YH, 0 ;[-14]
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| 265 | ldi cnt, 2 ;[-13]
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| 266 | ; rjmp usbSendAndReti fallthrough
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| 267 |
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| 268 | ;usbSend:
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| 269 | ;pointer to data in 'Y'
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| 270 | ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
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| 271 | ;uses: x1...x4, btcnt, shift, cnt, Y
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| 272 | ;Numbers in brackets are time since first bit of sync pattern is sent
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| 273 | ;We don't match the transfer rate exactly (don't insert leap cycles every third
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| 274 | ;byte) because the spec demands only 1.5% precision anyway.
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| 275 | usbSendAndReti: ; 12 cycles until SOP
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| 276 | in x2, USBDDR ;[-12]
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| 277 | ori x2, USBMASK ;[-11]
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| 278 | sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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| 279 | in x1, USBOUT ;[-8] port mirror for tx loop
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| 280 | out USBDDR, x2 ;[-7] <- acquire bus
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| 281 | ; need not init x2 (bitstuff history) because sync starts with 0
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| 282 | ldi x4, USBMASK ;[-6] exor mask
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| 283 | ldi shift, 0x80 ;[-5] sync byte is first byte sent
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| 284 | txByteLoop:
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| 285 | ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101
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| 286 | txBitLoop:
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| 287 | sbrs shift, 0 ;[-3] [7]
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| 288 | eor x1, x4 ;[-2] [8]
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| 289 | out USBOUT, x1 ;[-1] [9] <-- out N
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| 290 | ror shift ;[0] [10]
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| 291 | ror x2 ;[1]
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| 292 | didStuffN:
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| 293 | cpi x2, 0xfc ;[2]
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| 294 | brcc bitstuffN ;[3]
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| 295 | lsr bitcnt ;[4]
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| 296 | brcc txBitLoop ;[5]
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| 297 | brne txBitLoop ;[6]
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| 298 |
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| 299 | sbrs shift, 0 ;[7]
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| 300 | eor x1, x4 ;[8]
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| 301 | didStuff6:
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| 302 | out USBOUT, x1 ;[-1] [9] <-- out 6
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| 303 | ror shift ;[0] [10]
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| 304 | ror x2 ;[1]
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| 305 | cpi x2, 0xfc ;[2]
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| 306 | brcc bitstuff6 ;[3]
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| 307 | ror shift ;[4]
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| 308 | didStuff7:
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| 309 | ror x2 ;[5]
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| 310 | sbrs x2, 7 ;[6]
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| 311 | eor x1, x4 ;[7]
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| 312 | nop ;[8]
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| 313 | cpi x2, 0xfc ;[9]
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| 314 | out USBOUT, x1 ;[-1][10] <-- out 7
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| 315 | brcc bitstuff7 ;[0] [11]
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| 316 | ld shift, y+ ;[1]
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| 317 | dec cnt ;[3]
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| 318 | brne txByteLoop ;[4]
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| 319 | ;make SE0:
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| 320 | cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles]
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| 321 | lds x2, usbNewDeviceAddr;[6]
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| 322 | lsl x2 ;[8] we compare with left shifted address
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| 323 | subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3
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| 324 | sbci YH, 0 ;[10]
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| 325 | out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
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| 326 | ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
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| 327 | ;set address only after data packet was sent, not after handshake
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| 328 | breq skipAddrAssign ;[0]
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| 329 | sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
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| 330 | skipAddrAssign:
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| 331 | ;end of usbDeviceAddress transfer
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| 332 | ldi x2, 1<<USB_INTR_PENDING_BIT;[2] int0 occurred during TX -- clear pending flag
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| 333 | USB_STORE_PENDING(x2) ;[3]
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| 334 | ori x1, USBIDLE ;[4]
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| 335 | in x2, USBDDR ;[5]
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| 336 | cbr x2, USBMASK ;[6] set both pins to input
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| 337 | mov x3, x1 ;[7]
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| 338 | cbr x3, USBMASK ;[8] configure no pullup on both pins
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| 339 | ldi x4, 4 ;[9]
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| 340 | se0Delay:
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| 341 | dec x4 ;[10] [13] [16] [19]
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| 342 | brne se0Delay ;[11] [14] [17] [20]
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| 343 | out USBOUT, x1 ;[21] <-- out J (idle) -- end of SE0 (EOP signal)
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| 344 | out USBDDR, x2 ;[22] <-- release bus now
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| 345 | out USBOUT, x3 ;[23] <-- ensure no pull-up resistors are active
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| 346 | rjmp doReturn
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