| 1 | XT keyboard protocol and signalling
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| 2 | ===================================
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| 3 |
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| 4 | The keyboard comnmunicates with the PC/XT through a mostly single-direction
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| 5 | serial link.
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| 6 |
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| 7 | When the link is idle, the CLK line is high (floating), and the DATA line is
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| 8 | low (pulled by the keyboard).
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| 9 |
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| 10 | When the keyboard wants to send a byte:
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| 11 | - It checks that the CLK line is not pulled low (the PC/XT does this when the
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| 12 | receiving buffer is full).
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| 13 | - It sends the byte for the keycode. There is a start bit (DATA=1), followed by
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| 14 | the 7-bit keycode (LSb first), and the make/break bit (set for release, clear
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| 15 | for key press).
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| 16 |
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| 17 | As the 9th bit is pushed, the PC will force the clock line low until the CPU has
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| 18 | read the received byte and cleared the receiving register.
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| 19 |
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| 20 | The PC stores the data on the falling edge of the clock. It can also reset the
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| 21 | keyboard by pulling the clock line low for too long (unsure what the exact
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| 22 | timing is).
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| 23 |
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| 24 | It is up to the keyboard to manage the states of the LEDs. At power on, the LEDs
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| 25 | are off. They are switched by pressing CAPS and NUM locks. It's possible that
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| 26 | they get out of sync with the caps/num state the computer has. It is also up to
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| 27 | the keyboard to handle typematic (key repeat) and a keyboard buffer, if needed.
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| 28 |
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| 29 | At boot, the keyboard is supposed to send 0xAA when it is ready to work.
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| 30 | However, I'm not sure my XT clone BIOS actually checks for that.
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