[4b06930] | 1 | /* Name: usbdrvasm20.inc
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| 2 | * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
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| 3 | * Author: Jeroen Benschop
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| 4 | * Based on usbdrvasm16.inc from Christian Starkjohann
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| 5 | * Creation Date: 2008-03-05
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| 6 | * Tabsize: 4
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| 7 | * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH
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| 8 | * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
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| 9 | * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $
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| 10 | */
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| 11 |
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| 12 | /* Do not link this file! Link usbdrvasm.S instead, which includes the
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| 13 | * appropriate implementation!
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| 14 | */
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| 15 |
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| 16 | /*
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| 17 | General Description:
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| 18 | This file is the 20 MHz version of the asssembler part of the USB driver. It
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| 19 | requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC
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| 20 | oscillator).
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| 21 |
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| 22 | See usbdrv.h for a description of the entire driver.
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| 23 |
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| 24 | Since almost all of this code is timing critical, don't change unless you
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| 25 | really know what you are doing! Many parts require not only a maximum number
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| 26 | of CPU cycles, but even an exact number of cycles!
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| 27 | */
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| 28 |
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| 29 | #define leap2 x3
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| 30 | #ifdef __IAR_SYSTEMS_ASM__
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| 31 | #define nextInst $+2
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| 32 | #else
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| 33 | #define nextInst .+0
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| 34 | #endif
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| 35 |
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| 36 | ;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
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| 37 | ;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte
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| 38 | ; Numbers in brackets are clocks counted from center of last sync bit
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| 39 | ; when instruction starts
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| 40 | ;register use in receive loop:
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| 41 | ; shift assembles the byte currently being received
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| 42 | ; x1 holds the D+ and D- line state
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| 43 | ; x2 holds the previous line state
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| 44 | ; x4 (leap) is used to add a leap cycle once every three bytes received
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| 45 | ; X3 (leap2) is used to add a leap cycle once every three stuff bits received
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| 46 | ; bitcnt is used to determine when a stuff bit is due
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| 47 | ; cnt holds the number of bytes left in the receive buffer
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| 48 |
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| 49 | USB_INTR_VECTOR:
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| 50 | ;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
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| 51 | push YL ;[-28] push only what is necessary to sync with edge ASAP
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| 52 | in YL, SREG ;[-26]
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| 53 | push YL ;[-25]
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| 54 | push YH ;[-23]
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| 55 | ;----------------------------------------------------------------------------
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| 56 | ; Synchronize with sync pattern:
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| 57 | ;----------------------------------------------------------------------------
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| 58 | ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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| 59 | ;sync up with J to K edge during sync pattern -- use fastest possible loops
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| 60 | ;The first part waits at most 1 bit long since we must be in sync pattern.
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| 61 | ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
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| 62 | ;waitForJ, ensure that this prerequisite is met.
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| 63 | waitForJ:
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| 64 | inc YL
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| 65 | sbis USBIN, USBMINUS
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| 66 | brne waitForJ ; just make sure we have ANY timeout
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| 67 | waitForK:
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| 68 | ;The following code results in a sampling window of < 1/4 bit which meets the spec.
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| 69 | sbis USBIN, USBMINUS ;[-19]
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| 70 | rjmp foundK ;[-18]
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| 71 | sbis USBIN, USBMINUS
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| 72 | rjmp foundK
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| 73 | sbis USBIN, USBMINUS
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| 74 | rjmp foundK
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| 75 | sbis USBIN, USBMINUS
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| 76 | rjmp foundK
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| 77 | sbis USBIN, USBMINUS
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| 78 | rjmp foundK
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| 79 | sbis USBIN, USBMINUS
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| 80 | rjmp foundK
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| 81 | sbis USBIN, USBMINUS
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| 82 | rjmp foundK
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| 83 | sbis USBIN, USBMINUS
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| 84 | rjmp foundK
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| 85 | sbis USBIN, USBMINUS
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| 86 | rjmp foundK
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| 87 | #if USB_COUNT_SOF
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| 88 | lds YL, usbSofCount
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| 89 | inc YL
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| 90 | sts usbSofCount, YL
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| 91 | #endif /* USB_COUNT_SOF */
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| 92 | #ifdef USB_SOF_HOOK
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| 93 | USB_SOF_HOOK
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| 94 | #endif
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| 95 | rjmp sofError
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| 96 | foundK: ;[-16]
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| 97 | ;{3, 5} after falling D- edge, average delay: 4 cycles
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| 98 | ;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample
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| 99 | ;use 1 bit time for setup purposes, then sample again. Numbers in brackets
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| 100 | ;are cycles from center of first sync (double K) bit after the instruction
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| 101 | push bitcnt ;[-16]
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| 102 | ; [---] ;[-15]
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| 103 | lds YL, usbInputBufOffset;[-14]
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| 104 | ; [---] ;[-13]
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| 105 | clr YH ;[-12]
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| 106 | subi YL, lo8(-(usbRxBuf));[-11] [rx loop init]
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| 107 | sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init]
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| 108 | push shift ;[-9]
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| 109 | ; [---] ;[-8]
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| 110 | ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected
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| 111 | nop2 ;[-6]
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| 112 | ; [---] ;[-5]
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| 113 | ldi bitcnt, 5 ;[-4] [rx loop init]
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| 114 | sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early)
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| 115 | rjmp haveTwoBitsK ;[-2]
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| 116 | pop shift ;[-1] undo the push from before
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| 117 | pop bitcnt ;[1]
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| 118 | rjmp waitForK ;[3] this was not the end of sync, retry
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| 119 | ; The entire loop from waitForK until rjmp waitForK above must not exceed two
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| 120 | ; bit times (= 27 cycles).
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| 121 |
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| 122 | ;----------------------------------------------------------------------------
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| 123 | ; push more registers and initialize values while we sample the first bits:
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| 124 | ;----------------------------------------------------------------------------
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| 125 | haveTwoBitsK:
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| 126 | push x1 ;[0]
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| 127 | push x2 ;[2]
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| 128 | push x3 ;[4] (leap2)
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| 129 | ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit
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| 130 | push x4 ;[7] == leap
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| 131 | ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received
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| 132 | push cnt ;[10]
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| 133 | ldi cnt, USB_BUFSIZE ;[12] [rx loop init]
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| 134 | ldi x2, 1<<USBPLUS ;[13] current line state is K state. D+=="1", D-=="0"
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| 135 | bit0:
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| 136 | in x1, USBIN ;[0] sample line state
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| 137 | andi x1, USBMASK ;[1] filter only D+ and D- bits
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| 138 | rjmp handleBit ;[2] make bit0 14 cycles long
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| 139 |
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| 140 | ;----------------------------------------------------------------------------
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| 141 | ; Process bit7. However, bit 6 still may need unstuffing.
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| 142 | ;----------------------------------------------------------------------------
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| 143 |
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| 144 | b6checkUnstuff:
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| 145 | dec bitcnt ;[9]
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| 146 | breq unstuff6 ;[10]
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| 147 | bit7:
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| 148 | subi cnt, 1 ;[11] cannot use dec becaus it does not affect the carry flag
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| 149 | brcs overflow ;[12] Too many bytes received. Ignore packet
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| 150 | in x1, USBIN ;[0] sample line state
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| 151 | andi x1, USBMASK ;[1] filter only D+ and D- bits
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| 152 | cpse x1, x2 ;[2] when previous line state equals current line state, handle "1"
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| 153 | rjmp b7handle0 ;[3] when line state differs, handle "0"
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| 154 | sec ;[4]
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| 155 | ror shift ;[5] shift "1" into the data
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| 156 | st y+, shift ;[6] store the data into the buffer
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| 157 | ldi shift, 0x40 ;[7] reset data for receiving the next byte
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| 158 | subi leap, 0x55 ;[9] trick to introduce a leap cycle every 3 bytes
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| 159 | brcc nextInst ;[10 or 11] it will fail after 85 bytes. However low speed can only receive 11
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| 160 | dec bitcnt ;[11 or 12]
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| 161 | brne bit0 ;[12 or 13]
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| 162 | ldi x1, 1 ;[13 or 14] unstuffing bit 7
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| 163 | in bitcnt, USBIN ;[0] sample stuff bit
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| 164 | rjmp unstuff ;[1]
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| 165 |
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| 166 | b7handle0:
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| 167 | mov x2,x1 ;[5] Set x2 to current line state
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| 168 | ldi bitcnt, 6 ;[6]
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| 169 | lsr shift ;[7] shift "0" into the data
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| 170 | st y+, shift ;[8] store data into the buffer
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| 171 | ldi shift, 0x40 ;[10] reset data for receiving the next byte
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| 172 | subi leap, 0x55 ;[11] trick to introduce a leap cycle every 3 bytes
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| 173 | brcs bit0 ;[12] it will fail after 85 bytes. However low speed can only receive 11
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| 174 | rjmp bit0 ;[13]
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| 175 |
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| 176 |
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| 177 | ;----------------------------------------------------------------------------
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| 178 | ; Handle unstuff
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| 179 | ; x1==0xFF indicate unstuffing bit6
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| 180 | ;----------------------------------------------------------------------------
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| 181 |
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| 182 | unstuff6:
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| 183 | ldi x1,0xFF ;[12] indicate unstuffing bit 6
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| 184 | in bitcnt, USBIN ;[0] sample stuff bit
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| 185 | nop ;[1] fix timing
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| 186 | unstuff: ;b0-5 b6 b7
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| 187 | mov x2,bitcnt ;[3] [2] [3] Set x2 to match line state
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| 188 | subi leap2, 0x55 ;[4] [3] [4] delay loop
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| 189 | brcs nextInst ;[5] [4] [5] add one cycle every three stuff bits
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| 190 | sbci leap2,0 ;[6] [5] [6]
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| 191 | ldi bitcnt,6 ;[7] [6] [7] reset bit stuff counter
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| 192 | andi x2, USBMASK ;[8] [7] [8] only keep D+ and D-
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| 193 | cpi x1,0 ;[9] [8] [9]
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| 194 | brmi bit7 ;[10] [9] [10] finished unstuffing bit6 When x1<0
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| 195 | breq bitloop ;[11] --- [11] finished unstuffing bit0-5 when x1=0
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| 196 | nop ;--- --- [12]
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| 197 | in x1, USBIN ;--- --- [0] sample line state for bit0
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| 198 | andi x1, USBMASK ;--- --- [1] filter only D+ and D- bits
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| 199 | rjmp handleBit ;--- --- [2] make bit0 14 cycles long
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| 200 |
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| 201 | ;----------------------------------------------------------------------------
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| 202 | ; Receiver loop (numbers in brackets are cycles within byte after instr)
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| 203 | ;----------------------------------------------------------------------------
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| 204 | bitloop:
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| 205 | in x1, USBIN ;[0] sample line state
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| 206 | andi x1, USBMASK ;[1] filter only D+ and D- bits
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| 207 | breq se0 ;[2] both lines are low so handle se0
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| 208 | handleBit:
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| 209 | cpse x1, x2 ;[3] when previous line state equals current line state, handle "1"
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| 210 | rjmp handle0 ;[4] when line state differs, handle "0"
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| 211 | sec ;[5]
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| 212 | ror shift ;[6] shift "1" into the data
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| 213 | brcs b6checkUnstuff ;[7] When after shift C is set, next bit is bit7
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| 214 | nop2 ;[8]
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| 215 | dec bitcnt ;[10]
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| 216 | brne bitloop ;[11]
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| 217 | ldi x1,0 ;[12] indicate unstuff for bit other than bit6 or bit7
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| 218 | in bitcnt, USBIN ;[0] sample stuff bit
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| 219 | rjmp unstuff ;[1]
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| 220 |
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| 221 | handle0:
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| 222 | mov x2, x1 ;[6] Set x2 to current line state
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| 223 | ldi bitcnt, 6 ;[7] reset unstuff counter.
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| 224 | lsr shift ;[8] shift "0" into the data
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| 225 | brcs bit7 ;[9] When after shift C is set, next bit is bit7
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| 226 | nop ;[10]
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| 227 | rjmp bitloop ;[11]
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| 228 |
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| 229 | ;----------------------------------------------------------------------------
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| 230 | ; End of receive loop. Now start handling EOP
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| 231 | ;----------------------------------------------------------------------------
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| 232 |
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| 233 | macro POP_STANDARD ; 14 cycles
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| 234 | pop cnt
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| 235 | pop x4
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| 236 | pop x3
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| 237 | pop x2
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| 238 | pop x1
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| 239 | pop shift
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| 240 | pop bitcnt
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| 241 | endm
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| 242 | macro POP_RETI ; 7 cycles
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| 243 | pop YH
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| 244 | pop YL
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| 245 | out SREG, YL
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| 246 | pop YL
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| 247 | endm
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| 248 |
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| 249 |
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| 250 |
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| 251 | #include "asmcommon.inc"
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| 252 |
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| 253 | ; USB spec says:
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| 254 | ; idle = J
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| 255 | ; J = (D+ = 0), (D- = 1)
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| 256 | ; K = (D+ = 1), (D- = 0)
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| 257 | ; Spec allows 7.5 bit times from EOP to SOP for replies
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| 258 | ; 7.5 bit times is 100 cycles. This implementation arrives a bit later at se0
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| 259 | ; then specified in the include file but there is plenty of time
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| 260 |
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| 261 | bitstuffN:
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| 262 | eor x1, x4 ;[8]
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| 263 | ldi x2, 0 ;[9]
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| 264 | nop2 ;[10]
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| 265 | out USBOUT, x1 ;[12] <-- out
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| 266 | rjmp didStuffN ;[0]
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| 267 |
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| 268 | bitstuff7:
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| 269 | eor x1, x4 ;[6]
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| 270 | ldi x2, 0 ;[7] Carry is zero due to brcc
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| 271 | rol shift ;[8] compensate for ror shift at branch destination
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| 272 | nop2 ;[9]
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| 273 | rjmp didStuff7 ;[11]
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| 274 |
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| 275 | sendNakAndReti:
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| 276 | ldi x3, USBPID_NAK ;[-18]
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| 277 | rjmp sendX3AndReti ;[-17]
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| 278 | sendAckAndReti:
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| 279 | ldi cnt, USBPID_ACK ;[-17]
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| 280 | sendCntAndReti:
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| 281 | mov x3, cnt ;[-16]
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| 282 | sendX3AndReti:
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| 283 | ldi YL, 20 ;[-15] x3==r20 address is 20
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| 284 | ldi YH, 0 ;[-14]
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| 285 | ldi cnt, 2 ;[-13]
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| 286 | ; rjmp usbSendAndReti fallthrough
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| 287 |
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| 288 | ;usbSend:
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| 289 | ;pointer to data in 'Y'
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| 290 | ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
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| 291 | ;uses: x1...x4, btcnt, shift, cnt, Y
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| 292 | ;Numbers in brackets are time since first bit of sync pattern is sent
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| 293 | ;We don't match the transfer rate exactly (don't insert leap cycles every third
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| 294 | ;byte) because the spec demands only 1.5% precision anyway.
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| 295 | usbSendAndReti: ; 12 cycles until SOP
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| 296 | in x2, USBDDR ;[-12]
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| 297 | ori x2, USBMASK ;[-11]
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| 298 | sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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| 299 | in x1, USBOUT ;[-8] port mirror for tx loop
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| 300 | out USBDDR, x2 ;[-7] <- acquire bus
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| 301 | ; need not init x2 (bitstuff history) because sync starts with 0
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| 302 | ldi x4, USBMASK ;[-6] exor mask
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| 303 | ldi shift, 0x80 ;[-5] sync byte is first byte sent
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| 304 | txByteLoop:
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| 305 | ldi bitcnt, 0x49 ;[-4] [10] binary 01001001
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| 306 | txBitLoop:
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| 307 | sbrs shift, 0 ;[-3] [10] [11]
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| 308 | eor x1, x4 ;[-2] [11] [12]
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| 309 | out USBOUT, x1 ;[-1] [12] [13] <-- out N
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| 310 | ror shift ;[0] [13] [14]
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| 311 | ror x2 ;[1]
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| 312 | didStuffN:
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| 313 | nop2 ;[2]
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| 314 | nop ;[4]
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| 315 | cpi x2, 0xfc ;[5]
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| 316 | brcc bitstuffN ;[6]
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| 317 | lsr bitcnt ;[7]
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| 318 | brcc txBitLoop ;[8]
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| 319 | brne txBitLoop ;[9]
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| 320 |
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| 321 | sbrs shift, 0 ;[10]
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| 322 | eor x1, x4 ;[11]
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| 323 | didStuff7:
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| 324 | out USBOUT, x1 ;[-1] [13] <-- out 7
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| 325 | ror shift ;[0] [14]
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| 326 | ror x2 ;[1]
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| 327 | nop ;[2]
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| 328 | cpi x2, 0xfc ;[3]
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| 329 | brcc bitstuff7 ;[4]
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| 330 | ld shift, y+ ;[5]
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| 331 | dec cnt ;[7]
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| 332 | brne txByteLoop ;[8]
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| 333 | ;make SE0:
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| 334 | cbr x1, USBMASK ;[9] prepare SE0 [spec says EOP may be 25 to 30 cycles]
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| 335 | lds x2, usbNewDeviceAddr;[10]
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| 336 | lsl x2 ;[12] we compare with left shifted address
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| 337 | out USBOUT, x1 ;[13] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
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| 338 | subi YL, 20 + 2 ;[0] Only assign address on data packets, not ACK/NAK in x3
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| 339 | sbci YH, 0 ;[1]
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| 340 | ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
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| 341 | ;set address only after data packet was sent, not after handshake
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| 342 | breq skipAddrAssign ;[2]
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| 343 | sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
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| 344 | skipAddrAssign:
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| 345 | ;end of usbDeviceAddress transfer
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| 346 | ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
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| 347 | USB_STORE_PENDING(x2) ;[5]
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| 348 | ori x1, USBIDLE ;[6]
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| 349 | in x2, USBDDR ;[7]
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| 350 | cbr x2, USBMASK ;[8] set both pins to input
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| 351 | mov x3, x1 ;[9]
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| 352 | cbr x3, USBMASK ;[10] configure no pullup on both pins
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| 353 | ldi x4, 5 ;[11]
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| 354 | se0Delay:
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| 355 | dec x4 ;[12] [15] [18] [21] [24]
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| 356 | brne se0Delay ;[13] [16] [19] [22] [25]
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| 357 | out USBOUT, x1 ;[26] <-- out J (idle) -- end of SE0 (EOP signal)
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| 358 | out USBDDR, x2 ;[27] <-- release bus now
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| 359 | out USBOUT, x3 ;[28] <-- ensure no pull-up resistors are active
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| 360 | rjmp doReturn
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