Changeset cb32b0b in avrstuff


Ignore:
Timestamp:
Nov 14, 2010, 12:06:33 PM (13 years ago)
Author:
Adrien Destugues <pulkomandy@…>
Branches:
main
Children:
86824a6
Parents:
8f4b118
Message:
  • Code qui compile
  • Corrections sur le CI.

git-svn-id: svn://pulkomandy.tk/avrstuff@33 c6672c3c-f6b6-47f9-9001-1fd6b12fecbe

Location:
CPC stuff/cpc_serial_2313
Files:
6 added
1 edited

Legend:

Unmodified
Added
Removed
  • CPC stuff/cpc_serial_2313/code/main.asm

    r8f4b118 rcb32b0b  
    22; Copyright 2010, Adrien Destugues <pulkomandy@pulkomandy.ath.cx>
    33; Distributed under the terms of the MIT Licence
    4 .INCLUDE "2313def.inc"
    54
    65; Firmware for µSerial expansion board
    76
    8 .EQU ALL_OUT = 255
    9 .EQU ALL_IN = 0
    10 
    11 .EQU DATADIR = DDRB
    12 .EQU DATAOUT = PORTB
    13 .EQU DATAIN = PINB
    14 
    15 .EQU CTRLIN = PIND
    16 .EQU CTRLOUT = PORTD
    17 .EQU CTRLDIR = DDRD
    18 
    19 .EQU A0 = PIND5
    20 .EQU _READ = PIND3
    21 .EQU _WRITE = PIND2
    22 .EQU DEL = PIND6
    23 .EQU INT = PIND4
    24 
    25 .EQU curregbak = SRAM_START
    26 
    27 ; REGISTERS ALLOCATION
    28 ; R0 = 255 used in interrupt handler for fast switching of DATADIR
    29 ; X (R27 & R26) used in interrupt for fast addressing of regs
    30 
    31 .CSEG
    327; Vectors
    338; reset
    34         RJMP init
    359; int0
    3610        RJMP cpc_write
     
    5024
    5125; --- READ INTERRUPT ---
    52 cpc_read:
     26cpc_read
    5327; That means we only have 5 cycles left to output the value on the BUS!
    5428; We have no time to do anything, so we assume that X is already pointing at
     
    6438; We assume X (R26:R27) points to the current reg
    6539; So we can load it and react fast enough to the interrupt
    66         OUT DATADIR,R16         ; 1
    67         LD R27,X                        ; 2 cycles ; peut être économisé si un reg. contient
     40        LDI R0,ALL_OUT ; 1 ; peut être économisé si on sacrifie un reg
     41        OUT DATADIR,R0 ; 1
     42        LD R27,(X)                      ; 2 cycles ; peut être économisé si un reg. contient
    6843                                                                        ; déjà la valeur à envoyer
    6944                                                                        ; (mais qui l'update ?)
    70         OUT DATAOUT, R27        ; 1 cycle
     45        OUT DATA, R27           ; 1 cycle
    7146
    7247; Here data is sent, the CPC read operation is handled.
     
    7853
    7954; Restore R27
    80         LDS R27,curregbak
     55        LD R27,curregbak
     56        LD R27,(X)
    8157
    8258; release the bus
    83         SER R16
    84         OUT DATADIR, R16
    85         CLR R16
     59        LDI R0,ALL_IN
     60        OUT DATADIR, R0
    8661
    8762; Restore R27 to selected reg. (we erased it to do the OUT)
    8863        RETI
    8964
    90 
    9165; --- WRITE INTERRUPT ---
    92 cpc_write:
     66cpc_write
    9367; The timing is a bit less constraining here.
    94         PUSH R0                                         ; 2 cycles
    95         IN R0,DATAIN                            ; 1
     68        PUSH R0
     69        IN R0,DATA
    9670; we also need to know A0 state...
    97         SBIS CTRLIN,A0                          ; 1
     71        SBIS CTRL,A0
    9872                ; This was actually a reg select operation!
    9973                ; Jump to the proper code
     
    10579        RJMP intEnd
    10680
    107 regSel:
    108         STS curregbak,R0
     81regSel
     82        LD R27,curregbak
     83        ST (X),R0
    10984        MOV R27,R0
    11085
    111 intEnd:
    11286        POP R0
    11387        RETI
     
    11892; At a bare minimum :
    11993; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself
    120 init:
    121         CLI
    122         ; setup ctrl port : RW and A0 as inputs, INT and DEL as output
    123         LDI R16,0x28
    124         OUT CTRLDIR,R16
    125 
    126         ; setup dataport as input
    127         CLR R0
    128         OUT DATADIR,R0
    129 
    130         ; led on (will be turned off by software at init)
    131         SBI CTRLOUT,DEL
    132 
    133         ; init serial port speed and io
    134         LDI R16,10
    135         OUT UBRR,R16
    136 
    137         ; check for bootloader jumper and jump to bootload code if needed
    138         ; TODO
    139 
    140         ; setup interrupts (enable INT0 and INT1 on falling edge)
    141         LDI R16,0x0A
    142         OUT MCUCR,R16
    143 
    144         LDI R16,0xC0
    145         OUT GIMSK,R16
    146 
    147         ; we can now enable interrupts
    148         SEI
    149 
    150 mainloop:
    151         ; maybe we will have to handle a buffer for the serial port
    152         ; and 'fake' registers in SRAM
    153 
    154         SLEEP
    155         RJMP mainloop
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