Changeset cb32b0b in avrstuff
- Timestamp:
- Nov 14, 2010, 12:06:33 PM (13 years ago)
- Branches:
- main
- Children:
- 86824a6
- Parents:
- 8f4b118
- Location:
- CPC stuff/cpc_serial_2313
- Files:
-
- 6 added
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
CPC stuff/cpc_serial_2313/code/main.asm
r8f4b118 rcb32b0b 2 2 ; Copyright 2010, Adrien Destugues <pulkomandy@pulkomandy.ath.cx> 3 3 ; Distributed under the terms of the MIT Licence 4 .INCLUDE "2313def.inc"5 4 6 5 ; Firmware for µSerial expansion board 7 6 8 .EQU ALL_OUT = 2559 .EQU ALL_IN = 010 11 .EQU DATADIR = DDRB12 .EQU DATAOUT = PORTB13 .EQU DATAIN = PINB14 15 .EQU CTRLIN = PIND16 .EQU CTRLOUT = PORTD17 .EQU CTRLDIR = DDRD18 19 .EQU A0 = PIND520 .EQU _READ = PIND321 .EQU _WRITE = PIND222 .EQU DEL = PIND623 .EQU INT = PIND424 25 .EQU curregbak = SRAM_START26 27 ; REGISTERS ALLOCATION28 ; R0 = 255 used in interrupt handler for fast switching of DATADIR29 ; X (R27 & R26) used in interrupt for fast addressing of regs30 31 .CSEG32 7 ; Vectors 33 8 ; reset 34 RJMP init35 9 ; int0 36 10 RJMP cpc_write … … 50 24 51 25 ; --- READ INTERRUPT --- 52 cpc_read :26 cpc_read 53 27 ; That means we only have 5 cycles left to output the value on the BUS! 54 28 ; We have no time to do anything, so we assume that X is already pointing at … … 64 38 ; We assume X (R26:R27) points to the current reg 65 39 ; So we can load it and react fast enough to the interrupt 66 OUT DATADIR,R16 ; 1 67 LD R27,X ; 2 cycles ; peut être économisé si un reg. contient 40 LDI R0,ALL_OUT ; 1 ; peut être économisé si on sacrifie un reg 41 OUT DATADIR,R0 ; 1 42 LD R27,(X) ; 2 cycles ; peut être économisé si un reg. contient 68 43 ; déjà la valeur à envoyer 69 44 ; (mais qui l'update ?) 70 OUT DATA OUT, R27; 1 cycle45 OUT DATA, R27 ; 1 cycle 71 46 72 47 ; Here data is sent, the CPC read operation is handled. … … 78 53 79 54 ; Restore R27 80 LDS R27,curregbak 55 LD R27,curregbak 56 LD R27,(X) 81 57 82 58 ; release the bus 83 SER R16 84 OUT DATADIR, R16 85 CLR R16 59 LDI R0,ALL_IN 60 OUT DATADIR, R0 86 61 87 62 ; Restore R27 to selected reg. (we erased it to do the OUT) 88 63 RETI 89 64 90 91 65 ; --- WRITE INTERRUPT --- 92 cpc_write :66 cpc_write 93 67 ; The timing is a bit less constraining here. 94 PUSH R0 ; 2 cycles95 IN R0,DATA IN ; 168 PUSH R0 69 IN R0,DATA 96 70 ; we also need to know A0 state... 97 SBIS CTRL IN,A0 ; 171 SBIS CTRL,A0 98 72 ; This was actually a reg select operation! 99 73 ; Jump to the proper code … … 105 79 RJMP intEnd 106 80 107 regSel: 108 STS curregbak,R0 81 regSel 82 LD R27,curregbak 83 ST (X),R0 109 84 MOV R27,R0 110 85 111 intEnd:112 86 POP R0 113 87 RETI … … 118 92 ; At a bare minimum : 119 93 ; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself 120 init:121 CLI122 ; setup ctrl port : RW and A0 as inputs, INT and DEL as output123 LDI R16,0x28124 OUT CTRLDIR,R16125 126 ; setup dataport as input127 CLR R0128 OUT DATADIR,R0129 130 ; led on (will be turned off by software at init)131 SBI CTRLOUT,DEL132 133 ; init serial port speed and io134 LDI R16,10135 OUT UBRR,R16136 137 ; check for bootloader jumper and jump to bootload code if needed138 ; TODO139 140 ; setup interrupts (enable INT0 and INT1 on falling edge)141 LDI R16,0x0A142 OUT MCUCR,R16143 144 LDI R16,0xC0145 OUT GIMSK,R16146 147 ; we can now enable interrupts148 SEI149 150 mainloop:151 ; maybe we will have to handle a buffer for the serial port152 ; and 'fake' registers in SRAM153 154 SLEEP155 RJMP mainloop
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