Changeset df91872 in avrstuff for blinkled


Ignore:
Timestamp:
Apr 30, 2011, 9:37:02 AM (13 years ago)
Author:
Adrien Destugues <pulkomandy@…>
Branches:
main
Children:
13b28d3
Parents:
de0f65f
Message:
  • Blinkdel for attiny2313 (and easier to adapt)
  • Ramcard schematic update

git-svn-id: ​svn://pulkomandy.tk/avrstuff@36 c6672c3c-f6b6-47f9-9001-1fd6b12fecbe

Location:
blinkled
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • blinkled/Makefile

    rde0f65f rdf91872  
    11#Set vars
    2 COMPILE = avr-gcc -Wall -Os -std=c99 -mmcu=atmega8535 -DF_CPU=4000000
     2MCU=attiny2313
     3COMPILE = avr-gcc -Wall -Os -std=c99 -mmcu=$(MCU) -DF_CPU=20000000
    34
    45#Rules
    … …  
    2021
    2122flash:
    22         avrdude -c usbasp -p atmega8535 -Uflash:w:blinkdel.hex
     23        avrdude -c usbasp -p $(MCU) -Uflash:w:blinkdel.hex
    2324
    2425clean:

  • blinkled/blinkdel.hex

    rde0f65f rdf91872  
    1 :1000000014C01BC01AC019C018C017C016C015C034
    2 :1000100014C013C012C011C010C00FC00EC00DC05C
    3 :100020000CC00BC00AC009C008C011241FBECFE518
    4 :10003000D2E0DEBFCDBF02D01BC0E2CF2FE088E10F
    5 :1000400090E00FB6F894A89581BD0FBE21BD84E065
    6 :1000500083BF87B38FEF87BB8AEA88BB91E0A895FF
    7 :1000600008B600FEFCCF98BF88B38F5F88BBF7CF80
    8 :04007000F894FFCF32
     1:1000000012C017C016C015C014C013C012C011C052
     2:1000100010C00FC00EC00DC00CC00BC00AC009C07C
     3:1000200008C007C006C011241FBECFEDCDBF02D04F
     4:100030001CC0E6CF2FE088E190E00FB6F894A895B9
     5:1000400081BD0FBE21BD10BE84E083BF81B38FEFA1
     6:1000500081BB8AEA82BB92E0A89508B601FEFCCF7C
     7:0E00600098BF82B38F5F82BBF7CFF894FFCFBB
    98:00000001FF

  • blinkled/main.c

    rde0f65f rdf91872  
    1111        wdt_enable(WDTO_2S);
    1212    // configure timer 0 for a rate of 16M/(256 * 256) = ~244Hz
    13     TCCR0 = 4;          // timer 0 prescaler: 256
     13    TCCR0A = 0;          // timer 0 prescaler: 256
     14        TCCR0B = 4;
    1415
    1516        //debug LED - output
    16         DDRB |= 255;
     17        DDRD |= 255;
    1718
    18         PORTB = 0xAA;
     19        PORTD = 0xAA;
    1920
    2021        while(1) {
    … …  
    2526                if (TIFR & (1 << TOV0)) {
    2627                        TIFR = (1 << TOV0); // reset flag
    27                         PORTB++;
     28                        PORTD++;
    2829                }
    2930        }
Note: See TracChangeset for help on using the changeset viewer.