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The 6821 PIA

This is a generic I/O chip designed by Motorola and manufactured by Thomson as a second source. It is present in every Thomson machine.

Programming and architecture

Registers

The 6881 exposes 4 registers to the CPU. They are, in this order:

  • Data port A
  • Data port B
  • Control port A
  • Control port B

The control registers have the following functions:

Bit 7: interrpupt pin 1 state

This bit is set on transition (low>high or high>low) of the CA1 or CB1 pin. It is cleared by reading the output register.

Bit 6: interrpupt pin 2 state

This works the same as bit 7, but is only used when CA2 or CB2 is configured as an input pin. Otherwise, the pin can't be used as an interrupt source.

Bits 5-3: CA2/CB2 control

When bit 5 is 0, CA2/CB2 is set as an input pin, and can be used for interrupts. In this case, the two other bits have the following meaning:

  • bit 4: set this bit to emit interrupts on rising edges of CA2/CB2. Clear it to emit interrupts on the falling edges.
  • bit 3: Enable IRQA/B generation for CA2. When interrupts are disabled, bit 6 can still be used to poll the state of CA2/CB2.

When bit 5 is 1, CA2/CB2 is set as an output pin.

  • bit 4 set: the value of bit 3 is written to the pin
  • bit 4 clear: peripheral extension mode enabled. Bit 3 selects CA1/CB1 restore or E restore.

Bit 2: data register configuration

Setting this bit to 0 maps the data register to “direction configuration”. In this mode, writing to the data register allows configuring each bit as an output or input.

Setting it to 1 maps the output register instead, allowing to read and write the current level of the 8 bits on each port.

Peripheral expansion mode

In this mode, the PIA can be used to map other peripherals indirectly to the CPU bus. Pins CA2 and CB2 are used as read and write signal lines. This allows communication with slow peripherals, with the following scheme:

  • CA2 mirrors the “READ” signal decoded by the PIA. It goes low when output register A is read, and then goes high again either when the PIA is de-selected (“E-restore”), or when CA1 triggers an interrupt (“CA1-restore”).
  • CB2 mirrors the “WRITE” signal in a similar way. It goes low when output register B is written, and then goes high again either when the PIA is de-selected (“E-restore”), or when CB1 triggers an interrupt (“CB1-restore”).

Interrupts

Uses

MO "System" PIA

data port A

  • bit 0: /FORME - Switch the screen RAM mapping between pixel and attribute RAMs
  • bits 1-4: border color (R,G,B,P)
  • bit 5: light pen button
  • bit 6: tape drive data output
  • bit 7: tape drive data input

Bit 7 is low when no tape drive is plugged, and high when there is one. The monitor loading and saving code checks for this to detect the ape drive.

data port B

  • bit 0: sound output
  • bits 1-3: keyboard column to scan
  • bits 4-6: keyboard line to scan
  • bit 7: state of key selected by the column and line

Control ports

  • CA1: lightpen interrupt (IRQA is wired to 6809 FIRQ)
  • CA2: tape drive motor control (output)
  • CB1: 50Hz interrupt (IRQB is wired to 6809 IRQ)
  • CB2: video incrustation enable (output)

TO "System" PIA

Data port B

PB3-PB6: memory expansion control

These bits allows to map some of the expanded memory in TO machines. When no internal RAM is selected (bits are all 1), an external expansion (on the TO9) may be used. This is controlled by bits P2 and P6 of the 6846 PIA.

P6P2PB7PB6PB5PB4PB3Mapped memory at A000-DFFF
X X 1 1 1 X X TO7 32K expansion mappings
X X 1 1 1 1 0 Internal bank 0
X X 1 1 1 0 1 Internal bank 1
X X X X 0 1 1 TO9 extra internal RAM mappings
X X 0 0 0 1 1 Internal bank 2
X X 1 0 0 1 1 Internal bank 3
X X 0 1 0 1 1 Internal bank 4
X X 1 1 0 1 1 Internal bank 5
X X 1 1 1 1 1 TO9 external RAM mappings
0 0 1 1 1 1 1 RAMdisk 1
1 0 1 1 1 1 1 RAMdisk 2
0 1 1 1 1 1 1 RAMdisk 3
1 1 1 1 1 1 1 RAMdisk 4

Seriously, this system is a mess. Use the new banking from the gate array if you can.

"Sound and Games" PIA

Data port A

  • Joystick reading

Data port B

  • DAC output (6 bits)
  • Player 2 action button

Control ports

  • CA1: player 1 action button
  • CB1: player 2 action button

Documents

documentations/devices/6821.1395782952.txt.gz · Last modified: 2015/02/28 18:08 (external edit)
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