blob: 07b61d9df80736068f6013ed7d0f9b67c3d0718f [file] [log] [blame]
# EESchema Netlist Version 1.1 created 30/04/2011 21:32:23
(
( /4CA8A6F2 $noname U1 74LS00 {Lib=74LS00}
( 1 /A15 )
( 2 /A14 )
( 3 ROM_ACC )
( 4 N-000020 )
( 5 N-000020 )
( 6 N-000076 )
( 7 GND )
( 8 _A3 )
( 9 A3 )
( 10 A3 )
( 14 VCC )
)
( /4CA89162 $noname U3 74LS32 {Lib=74LS32}
( 1 /A13 )
( 2 N-000026 )
( 3 ROMSEL )
( 4 IORQ )
( 5 WR )
( 6 N-000026 )
( 7 GND )
( 8 N-000020 )
( 9 ROM_ACTIVE )
( 10 ROMEN )
( 11 WRITE_EN )
( 12 WR )
( 13 ROM_ACTIVE )
( 14 VCC )
)
( /4CA87798 $noname BT1 CR2032 {Lib=BATTERY}
( 1 N-000075 )
( 2 GND )
)
( /4CA871FB $noname U6 SRAM_512KO {Lib=SRAM_512KO}
( 1 ? )
( 2 ? )
( 3 /A14 )
( 4 /A13 )
( 5 /A11 )
( 6 /A9 )
( 7 /A7 )
( 8 /A5 )
( 9 A3 )
( 10 /A2 )
( 11 /A1 )
( 12 /A0 )
( 13 /D2 )
( 14 /D5 )
( 15 /D7 )
( 16 GND )
( 17 /D4 )
( 18 /D6 )
( 19 /D3 )
( 20 /D1 )
( 21 /D0 )
( 22 N-000003 )
( 23 /A4 )
( 24 ROM_ACTIVE )
( 25 /A6 )
( 26 /A8 )
( 27 /A10 )
( 28 /A12 )
( 29 WRITE )
( 30 +BATT )
( 31 /A15 )
( 32 +BATT )
)
( /4CA87175 $noname Q1 BC307 {Lib=BC307}
( B N-000066 )
( C N-000003 )
( E GND )
)
( /4CA87152 $noname C4 C {Lib=C}
( 1 ? )
( 2 ? )
)
( /4CA87151 $noname C3 C {Lib=C}
( 1 ? )
( 2 ? )
)
( /4CA87148 $noname C1 1ยตF {Lib=CP1}
( 1 N-000090 )
( 2 GND )
)
( /4CA87146 $noname C5 CP1 {Lib=CP1}
( 1 ? )
( 2 ? )
)
( /4CA8712F $noname P1 CONN_25X2 {Lib=CONN_25X2}
( 1 ? )
( 2 ? )
( 3 /A15 )
( 4 /A14 )
( 5 /A13 )
( 6 /A12 )
( 7 /A11 )
( 8 /A10 )
( 9 /A9 )
( 10 /A8 )
( 11 /A7 )
( 12 /A6 )
( 13 /A5 )
( 14 /A4 )
( 15 A3 )
( 16 /A2 )
( 17 /A1 )
( 18 /A0 )
( 19 /D0 )
( 20 /D1 )
( 21 /D2 )
( 22 /D3 )
( 23 /D4 )
( 24 /D5 )
( 25 /D6 )
( 26 /D7 )
( 27 VCC )
( 28 ? )
( 29 ? )
( 30 ? )
( 31 IORQ )
( 32 ? )
( 33 WR )
( 34 ? )
( 35 ? )
( 36 ? )
( 37 ? )
( 38 ? )
( 39 ? )
( 40 ? )
( 41 ? )
( 42 ROMEN )
( 43 ROMDIS )
( 44 ? )
( 45 ? )
( 46 ? )
( 47 ? )
( 48 ? )
( 49 GND )
( 50 ? )
)
( /4CA870EF $noname C2 C {Lib=C}
( 1 +BATT )
( 2 GND )
)
( /4CA870E2 $noname R9 R {Lib=R}
( 1 A3 )
( 2 N-000065 )
)
( /4CA870DC $noname R1 10K {Lib=R}
( 1 N-000066 )
( 2 GND )
)
( /4CA870DB $noname R7 1K {Lib=R}
( 1 VCC )
( 2 N-000090 )
)
( /4CA870DA $noname R10 R {Lib=R}
( 1 +BATT )
( 2 N-000003 )
)
( /4CA870D9 $noname R2 10KR {Lib=R}
( 1 WRITE )
( 2 VCC )
)
( /4CA870D8 $noname R6 10KR {Lib=R}
( 1 VCC )
( 2 /I4 )
)
( /4CA870D0 $noname R5 10KR {Lib=R}
( 1 VCC )
( 2 /I3 )
)
( /4CA870CB $noname R4 10KR {Lib=R}
( 1 VCC )
( 2 /I2 )
)
( /4CA870C7 $noname R3 10KR {Lib=R}
( 1 VCC )
( 2 /I1 )
)
( /4CA870C2 $noname R8 R {Lib=R}
( 1 VCC )
( 2 ROM_ACTIVE )
)
( /4CA870B3 $noname D11 DIODE {Lib=DIODE}
( 1 VCC )
( 2 +BATT )
)
( /4CA870AF $noname D1 1N4148 {Lib=DIODE}
( 1 N-000090 )
( 2 VCC )
)
( /4CA870AC $noname D12 BAT85 {Lib=DIODE}
( 1 N-000075 )
( 2 +BATT )
)
( /4CA870AA $noname D13 DIODE {Lib=DIODE}
( 1 N-000076 )
( 2 ROMDIS )
)
( /4CA870A4 $noname D2 BZX55C {Lib=DIODE}
( 1 N-000066 )
( 2 N-000090 )
)
( /4CA8709A $noname D10 DIODE {Lib=DIODE}
( 1 ROM_ACTIVE )
( 2 N-000078 )
)
( /4CA87098 $noname D9 DIODE {Lib=DIODE}
( 1 ROM_ACTIVE )
( 2 N-000079 )
)
( /4CA87095 $noname D8 DIODE {Lib=DIODE}
( 1 ROM_ACTIVE )
( 2 N-000080 )
)
( /4CA87093 $noname D7 DIODE {Lib=DIODE}
( 1 ROM_ACTIVE )
( 2 N-000081 )
)
( /4CA87092 $noname D6 DIODE {Lib=DIODE}
( 1 ROM_ACTIVE )
( 2 N-000082 )
)
( /4CA87090 $noname D5 DIODE {Lib=DIODE}
( 1 ROM_ACTIVE )
( 2 N-000083 )
)
( /4CA8708D $noname D4 DIODE {Lib=DIODE}
( 1 ROM_ACTIVE )
( 2 N-000084 )
)
( /4CA87086 $noname D3 DIODE {Lib=DIODE}
( 1 ROM_ACTIVE )
( 2 N-000085 )
)
( /4CA87071 $noname SW_CFG1 DIPS_08 {Lib=DIPS_08}
( 1 /I1 )
( 2 /I2 )
( 3 /I3 )
( 4 /I4 )
( 5 N-000065 )
( 6 ? )
( 7 ? )
( 8 WRITE )
( 9 WRITE_EN )
( 10 ? )
( 11 ? )
( 12 _A3 )
( 13 GND )
( 14 GND )
( 15 GND )
( 16 GND )
)
( /4CA8706E $noname SW_ROMEN1 DIPS_08 {Lib=DIPS_08}
( 1 N-000072 )
( 2 N-000073 )
( 3 N-000074 )
( 4 N-000049 )
( 5 N-000048 )
( 6 N-000047 )
( 7 N-000046 )
( 8 N-000045 )
( 9 N-000078 )
( 10 N-000079 )
( 11 N-000080 )
( 12 N-000081 )
( 13 N-000082 )
( 14 N-000083 )
( 15 N-000084 )
( 16 N-000085 )
)
( /4CA86E70 $noname U5 74LS85 {Lib=74LS85}
( 1 /I3 )
( 2 ? )
( 3 N-000065 )
( 4 ? )
( 5 ? )
( 6 MATCH )
( 7 ? )
( 8 GND )
( 9 /AC3 )
( 10 /I4 )
( 11 /I1 )
( 12 /AC0 )
( 13 /I2 )
( 14 /AC1 )
( 15 /AC2 )
( 16 VCC )
)
( /4CA86E68 $noname U4 74LS374 {Lib=74LS374}
( 1 GND )
( 2 /IS0 )
( 3 /D0 )
( 4 /D1 )
( 5 /IS1 )
( 6 /AC3 )
( 7 /D6 )
( 8 /D4 )
( 9 /AC1 )
( 10 GND )
( 11 ROMSEL )
( 12 /AC0 )
( 13 /D3 )
( 14 /D5 )
( 15 /AC2 )
( 16 /IS2 )
( 17 /D2 )
( 18 /D7 )
( 19 A3 )
( 20 VCC )
)
( /4CA86E2A $noname U2 74LS138 {Lib=74LS138}
( 1 /IS0 )
( 2 /IS1 )
( 3 /IS2 )
( 4 ? )
( 5 ROM_ACC )
( 6 MATCH )
( 7 N-000045 )
( 8 GND )
( 9 N-000046 )
( 10 N-000047 )
( 11 N-000048 )
( 12 N-000049 )
( 13 N-000074 )
( 14 N-000073 )
( 15 N-000072 )
( 16 VCC )
)
)
*
{ Allowed footprints by component:
$component U1
14DIP300*
SO14*
$endlist
$component Q1
TO92-EBC
$endlist
$component C4
SM*
C?
C1-1
$endlist
$component C3
SM*
C?
C1-1
$endlist
$component C1
CP*
SM*
$endlist
$component C5
CP*
SM*
$endlist
$component C2
SM*
C?
C1-1
$endlist
$component R9
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R1
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R7
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R10
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R2
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R6
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R5
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R4
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R3
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component R8
R?
SM0603
SM0805
R?-*
SM1206
$endlist
$component D11
D?
S*
$endlist
$component D1
D?
S*
$endlist
$component D12
D?
S*
$endlist
$component D13
D?
S*
$endlist
$component D2
D?
S*
$endlist
$component D10
D?
S*
$endlist
$component D9
D?
S*
$endlist
$component D8
D?
S*
$endlist
$component D7
D?
S*
$endlist
$component D6
D?
S*
$endlist
$component D5
D?
S*
$endlist
$component D4
D?
S*
$endlist
$component D3
D?
S*
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "/D1" "D1"
U4 4
P1 20
U6 20
Net 2 "/D0" "D0"
U4 3
U6 21
P1 19
Net 3 "" ""
Q1 C
U6 22
R10 2
Net 4 "/D2" "D2"
U4 17
U6 13
P1 21
Net 5 "/D4" "D4"
P1 23
U6 17
U4 8
Net 6 "/D3" "D3"
U4 13
P1 22
U6 19
Net 7 "GND" "GND"
U2 8
P1 49
C2 2
U5 8
U3 7
R1 2
U1 7
U6 16
U4 1
C1 2
U4 10
Q1 E
SW_CFG1 13
SW_CFG1 14
SW_CFG1 15
SW_CFG1 16
BT1 2
Net 8 "VCC" "VCC"
U2 16
U5 16
U4 20
R7 1
R2 2
R6 1
R5 1
R4 1
R3 1
R8 1
D11 1
D1 2
P1 27
U1 14
U3 14
Net 19 "ROM_ACTIVE" "ROM_ACTIVE"
D6 1
D7 1
D8 1
D9 1
D10 1
R8 2
D5 1
U3 13
D4 1
D3 1
U6 24
U3 9
Net 20 "" ""
U3 8
U1 5
U1 4
Net 21 "ROMEN" "ROMEN"
P1 42
U3 10
Net 25 "/A13" "A13"
U3 1
P1 5
U6 4
Net 26 "" ""
U3 6
U3 2
Net 27 "WRITE" "WRITE"
R2 1
U6 29
SW_CFG1 8
Net 31 "IORQ" "IORQ"
P1 31
U3 4
Net 33 "MATCH" "MATCH"
U2 6
U5 6
Net 35 "/AC3" "AC3"
U5 9
U4 6
Net 36 "/AC0" "AC0"
U4 12
U5 12
Net 37 "/AC1" "AC1"
U5 14
U4 9
Net 38 "/AC2" "AC2"
U4 15
U5 15
Net 41 "/A15" "A15"
U6 31
P1 3
U1 1
Net 42 "/A14" "A14"
P1 4
U1 2
U6 3
Net 44 "ROM_ACC" "ROM_ACC"
U2 5
U1 3
Net 45 "" ""
U2 7
SW_ROMEN1 8
Net 46 "" ""
U2 9
SW_ROMEN1 7
Net 47 "" ""
U2 10
SW_ROMEN1 6
Net 48 "" ""
U2 11
SW_ROMEN1 5
Net 49 "" ""
U2 12
SW_ROMEN1 4
Net 50 "ROMSEL" "ROMSEL"
U3 3
U4 11
Net 51 "WRITE_EN" "WRITE_EN"
U3 11
SW_CFG1 9
Net 52 "WR" "WR"
P1 33
U3 5
U3 12
Net 53 "+BATT" "+BATT"
D12 2
C2 1
D11 2
R10 1
U6 30
U6 32
Net 64 "A3" "A3"
R9 1
P1 15
U6 9
U4 19
U1 9
U1 10
Net 65 "" ""
U5 3
R9 2
SW_CFG1 5
Net 66 "" ""
D2 1
Q1 B
R1 1
Net 71 "_A3" "_A3"
U1 8
SW_CFG1 12
Net 72 "" ""
SW_ROMEN1 1
U2 15
Net 73 "" ""
SW_ROMEN1 2
U2 14
Net 74 "" ""
SW_ROMEN1 3
U2 13
Net 75 "" ""
D12 1
BT1 1
Net 76 "" ""
U1 6
D13 1
Net 77 "ROMDIS" "ROMDIS"
P1 43
D13 2
Net 78 "" ""
D10 2
SW_ROMEN1 9
Net 79 "" ""
D9 2
SW_ROMEN1 10
Net 80 "" ""
D8 2
SW_ROMEN1 11
Net 81 "" ""
D7 2
SW_ROMEN1 12
Net 82 "" ""
D6 2
SW_ROMEN1 13
Net 83 "" ""
SW_ROMEN1 14
D5 2
Net 84 "" ""
SW_ROMEN1 15
D4 2
Net 85 "" ""
D3 2
SW_ROMEN1 16
Net 86 "/I4" "I4"
R6 2
U5 10
SW_CFG1 4
Net 87 "/I3" "I3"
U5 1
SW_CFG1 3
R5 2
Net 88 "/I2" "I2"
U5 13
R4 2
SW_CFG1 2
Net 89 "/I1" "I1"
U5 11
R3 2
SW_CFG1 1
Net 90 "" ""
D2 2
C1 1
R7 2
D1 1
Net 91 "/IS2" "IS2"
U4 16
U2 3
Net 92 "/IS1" "IS1"
U4 5
U2 2
Net 93 "/IS0" "IS0"
U4 2
U2 1
Net 96 "/A12" "A12"
P1 6
U6 28
Net 97 "/A11" "A11"
P1 7
U6 5
Net 98 "/A10" "A10"
U6 27
P1 8
Net 99 "/A9" "A9"
U6 6
P1 9
Net 100 "/A8" "A8"
P1 10
U6 26
Net 101 "/A7" "A7"
U6 7
P1 11
Net 102 "/A6" "A6"
P1 12
U6 25
Net 103 "/A5" "A5"
P1 13
U6 8
Net 104 "/D6" "D6"
P1 25
U6 18
U4 7
Net 105 "/D5" "D5"
U6 14
P1 24
U4 14
Net 106 "/D7" "D7"
U6 15
P1 26
U4 18
Net 107 "/A4" "A4"
U6 23
P1 14
Net 108 "/A2" "A2"
P1 16
U6 10
Net 109 "/A1" "A1"
U6 11
P1 17
Net 110 "/A0" "A0"
P1 18
U6 12
}
#End