Index: ledclock/circuit/ledclock/conn_te_micromatch.pretty/TE_MicroMatch_215750-0016_2x08_P1.27mm_Vertical.kicad_mod
===================================================================
--- ledclock/circuit/ledclock/conn_te_micromatch.pretty/TE_MicroMatch_215750-0016_2x08_P1.27mm_Vertical.kicad_mod	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
+++ ledclock/circuit/ledclock/conn_te_micromatch.pretty/TE_MicroMatch_215750-0016_2x08_P1.27mm_Vertical.kicad_mod	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
@@ -0,0 +1,49 @@
+(module TE_MicroMatch_215750-0016_2x08_P1.27mm_Vertical (layer F.Cu) (tedit 5E9F481C)
+  (descr "TE Connectivity MicroMatch")
+  (tags "connector AMP TE MicroMatch side entry")
+  (fp_text reference J1 (at -0.635 -1.905 180) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value Conn_01x12_Male (at -2.54 8.89 90) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start -1.48 -1.27) (end 3.52 -1.27) (layer F.Fab) (width 0.1))
+  (fp_line (start -1.61 -1.38) (end 3.65 -1.38) (layer F.SilkS) (width 0.12))
+  (fp_line (start 3.52 -1.27) (end 3.52 20.3) (layer F.Fab) (width 0.1))
+  (fp_line (start 3.65 -1.38) (end 3.65 20.41) (layer F.SilkS) (width 0.12))
+  (fp_line (start 3.52 20.3) (end -1.48 20.3) (layer F.Fab) (width 0.1))
+  (fp_line (start 3.65 20.41) (end -1.61 20.41) (layer F.SilkS) (width 0.12))
+  (fp_line (start -1.48 -1.27) (end -1.48 -0.5) (layer F.Fab) (width 0.1))
+  (fp_line (start -1.48 -0.5) (end -0.98 0) (layer F.Fab) (width 0.1))
+  (fp_line (start -0.98 0) (end -1.48 0.5) (layer F.Fab) (width 0.1))
+  (fp_line (start -1.48 0.5) (end -1.48 20.3) (layer F.Fab) (width 0.1))
+  (fp_line (start -1.61 -1.38) (end -1.61 20.4) (layer F.SilkS) (width 0.12))
+  (fp_line (start 1.145 0) (end 1.745 0.3) (layer F.SilkS) (width 0.12))
+  (fp_line (start 1.745 0.3) (end 1.745 -0.3) (layer F.SilkS) (width 0.12))
+  (fp_line (start 1.745 -0.3) (end 1.145 0) (layer F.SilkS) (width 0.12))
+  (fp_text user %R (at -0.635 -1.905) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (pad 1 thru_hole roundrect (at 0 0) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask) (roundrect_rratio 0.192308))
+  (pad 3 thru_hole oval (at 0 2.54) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 5 thru_hole oval (at 0 5.08) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 7 thru_hole oval (at 0 7.62) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 9 thru_hole oval (at 0 10.16) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 11 thru_hole oval (at 0 12.7) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 13 thru_hole oval (at 0 15.24) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 15 thru_hole oval (at 0 17.78) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 2 thru_hole oval (at 2.54 1.27) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 4 thru_hole oval (at 2.54 3.81) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 6 thru_hole oval (at 2.54 6.35) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 8 thru_hole oval (at 2.54 8.89) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 10 thru_hole oval (at 2.54 11.43) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 12 thru_hole oval (at 2.54 13.97) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 14 thru_hole oval (at 2.54 16.51) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad 16 thru_hole oval (at 2.54 19.05) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+  (pad "" np_thru_hole circle (at 1.8 -1.4) (size 1.5 1.5) (drill 1.5) (layers *.Cu *.Mask))
+  (model ${KISYS3DMOD}/Connector_Molex.3dshapes/Molex_Picoflex_90325-0016_2x08_P1.27mm_Vertical.wrl
+    (at (xyz 0 0 0))
+    (scale (xyz 1 1 1))
+    (rotate (xyz 0 0 0))
+  )
+)
Index: ledclock/circuit/ledclock/fp-lib-table
===================================================================
--- ledclock/circuit/ledclock/fp-lib-table	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
+++ ledclock/circuit/ledclock/fp-lib-table	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
@@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name conn_te_micromatch)(type KiCad)(uri ${KIPRJMOD}/conn_te_micromatch.pretty)(options "")(descr ""))
+)
Index: ledclock/circuit/ledclock/ledclock-cache.lib
===================================================================
--- ledclock/circuit/ledclock/ledclock-cache.lib	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
+++ ledclock/circuit/ledclock/ledclock-cache.lib	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
@@ -0,0 +1,137 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# 74xx_74HC595
+#
+DEF 74xx_74HC595 U 0 20 Y Y 1 F N
+F0 "U" -300 550 50 H V C CNN
+F1 "74xx_74HC595" -300 -650 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS 74LS595 74HCT595
+$FPLIST
+ DIP*W7.62mm*
+ SOIC*3.9x9.9mm*P1.27mm*
+ TSSOP*4.4x5mm*P0.65mm*
+ SOIC*5.3x10.2mm*P1.27mm*
+ SOIC*7.5x10.3mm*P1.27mm*
+$ENDFPLIST
+DRAW
+S -300 500 300 -600 1 1 10 f
+X QB 1 400 300 100 L 50 50 1 0 T
+X ~SRCLR 10 -400 100 100 R 50 50 1 0 I
+X SRCLK 11 -400 200 100 R 50 50 1 0 I
+X RCLK 12 -400 -100 100 R 50 50 1 0 I
+X ~OE 13 -400 -200 100 R 50 50 1 0 I
+X SER 14 -400 400 100 R 50 50 1 0 I
+X QA 15 400 400 100 L 50 50 1 0 T
+X VCC 16 0 600 100 D 50 50 1 0 W
+X QC 2 400 200 100 L 50 50 1 0 T
+X QD 3 400 100 100 L 50 50 1 0 T
+X QE 4 400 0 100 L 50 50 1 0 T
+X QF 5 400 -100 100 L 50 50 1 0 T
+X QG 6 400 -200 100 L 50 50 1 0 T
+X QH 7 400 -300 100 L 50 50 1 0 T
+X GND 8 0 -700 100 U 50 50 1 0 W
+X QH' 9 400 -500 100 L 50 50 1 0 O
+ENDDRAW
+ENDDEF
+#
+# Connector_Conn_01x12_Male
+#
+DEF Connector_Conn_01x12_Male J 0 40 Y N 1 F N
+F0 "J" 0 600 50 H V C CNN
+F1 "Connector_Conn_01x12_Male" 0 -700 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S 34 -595 0 -605 1 1 6 F
+S 34 -495 0 -505 1 1 6 F
+S 34 -395 0 -405 1 1 6 F
+S 34 -295 0 -305 1 1 6 F
+S 34 -195 0 -205 1 1 6 F
+S 34 -95 0 -105 1 1 6 F
+S 34 5 0 -5 1 1 6 F
+S 34 105 0 95 1 1 6 F
+S 34 205 0 195 1 1 6 F
+S 34 305 0 295 1 1 6 F
+S 34 405 0 395 1 1 6 F
+S 34 505 0 495 1 1 6 F
+P 2 1 1 6 50 -600 34 -600 N
+P 2 1 1 6 50 -500 34 -500 N
+P 2 1 1 6 50 -400 34 -400 N
+P 2 1 1 6 50 -300 34 -300 N
+P 2 1 1 6 50 -200 34 -200 N
+P 2 1 1 6 50 -100 34 -100 N
+P 2 1 1 6 50 0 34 0 N
+P 2 1 1 6 50 100 34 100 N
+P 2 1 1 6 50 200 34 200 N
+P 2 1 1 6 50 300 34 300 N
+P 2 1 1 6 50 400 34 400 N
+P 2 1 1 6 50 500 34 500 N
+X Pin_1 1 200 500 150 L 50 50 1 1 P
+X Pin_10 10 200 -400 150 L 50 50 1 1 P
+X Pin_11 11 200 -500 150 L 50 50 1 1 P
+X Pin_12 12 200 -600 150 L 50 50 1 1 P
+X Pin_2 2 200 400 150 L 50 50 1 1 P
+X Pin_3 3 200 300 150 L 50 50 1 1 P
+X Pin_4 4 200 200 150 L 50 50 1 1 P
+X Pin_5 5 200 100 150 L 50 50 1 1 P
+X Pin_6 6 200 0 150 L 50 50 1 1 P
+X Pin_7 7 200 -100 150 L 50 50 1 1 P
+X Pin_8 8 200 -200 150 L 50 50 1 1 P
+X Pin_9 9 200 -300 150 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Transistor_Array_ULN2003
+#
+DEF Transistor_Array_ULN2003 U 0 20 Y Y 1 F N
+F0 "U" 0 625 50 H V C CNN
+F1 "Transistor_Array_ULN2003" 0 550 50 H V C CNN
+F2 "" 50 -550 50 H I L CNN
+F3 "" 100 -200 50 H I C CNN
+ALIAS ULN2003A ULN2002 ULN2002A ULN2004 ULN2004A
+$FPLIST
+ DIP*W7.62mm*
+ SOIC*3.9x9.9mm*P1.27mm*
+ SSOP*4.4x5.2mm*P0.65mm*
+ TSSOP*4.4x5mm*P0.65mm*
+ SOIC*W*5.3x10.2mm*P1.27mm*
+$ENDFPLIST
+DRAW
+C -70 200 10 0 1 0 N
+C -50 -90 10 0 1 0 F
+C -50 0 10 0 1 0 F
+C -50 100 10 0 1 0 F
+C -20 200 10 0 1 0 F
+S -300 -500 300 500 0 1 10 f
+P 2 0 1 0 -180 200 -140 200 N
+P 2 0 1 0 -60 200 160 200 N
+P 2 0 1 0 0 265 -40 265 N
+P 3 0 1 0 -20 200 -20 400 115 400 N
+P 4 0 1 0 -140 240 -140 160 -80 200 -140 240 N
+P 4 0 1 0 0 235 -40 235 -20 265 0 235 N
+X I1 1 -400 200 100 R 50 50 1 1 I
+X O7 10 400 -400 100 L 50 50 1 1 C
+X O6 11 400 -300 100 L 50 50 1 1 C
+X O5 12 400 -200 100 L 50 50 1 1 C
+X O4 13 400 -100 100 L 50 50 1 1 C
+X O3 14 400 0 100 L 50 50 1 1 C
+X O2 15 400 100 100 L 50 50 1 1 C
+X O1 16 400 200 100 L 50 50 1 1 C
+X I2 2 -400 100 100 R 50 50 1 1 I
+X I3 3 -400 0 100 R 50 50 1 1 I
+X I4 4 -400 -100 100 R 50 50 1 1 I
+X I5 5 -400 -200 100 R 50 50 1 1 I
+X I6 6 -400 -300 100 R 50 50 1 1 I
+X I7 7 -400 -400 100 R 50 50 1 1 I
+X GND 8 0 -600 100 U 50 50 1 1 W
+X COM 9 400 400 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
Index: ledclock/circuit/ledclock/ledclock.kicad_pcb
===================================================================
--- ledclock/circuit/ledclock/ledclock.kicad_pcb	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
+++ ledclock/circuit/ledclock/ledclock.kicad_pcb	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
@@ -0,0 +1,496 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.0.2+dfsg1-1)
+
+  (general
+    (thickness 1.6)
+    (drawings 16)
+    (tracks 112)
+    (zones 0)
+    (modules 3)
+    (nets 20)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (segment_width 0.2)
+    (edge_width 0.15)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 /S1)
+  (net 2 /S3)
+  (net 3 /S5)
+  (net 4 /S7)
+  (net 5 /VCC)
+  (net 6 /SCLK)
+  (net 7 /S2)
+  (net 8 /S4)
+  (net 9 /S6)
+  (net 10 /GND)
+  (net 11 /SIN)
+  (net 12 /SOUT)
+  (net 13 "Net-(U1-Pad1)")
+  (net 14 "Net-(U1-Pad2)")
+  (net 15 "Net-(U1-Pad3)")
+  (net 16 "Net-(U1-Pad4)")
+  (net 17 "Net-(U1-Pad5)")
+  (net 18 "Net-(U1-Pad6)")
+  (net 19 "Net-(U1-Pad15)")
+
+  (net_class Default "Ceci est la Netclass par défaut."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net /GND)
+    (add_net /S1)
+    (add_net /S2)
+    (add_net /S3)
+    (add_net /S4)
+    (add_net /S5)
+    (add_net /S6)
+    (add_net /S7)
+    (add_net /SCLK)
+    (add_net /SIN)
+    (add_net /SOUT)
+    (add_net /VCC)
+    (add_net "Net-(U1-Pad1)")
+    (add_net "Net-(U1-Pad15)")
+    (add_net "Net-(U1-Pad2)")
+    (add_net "Net-(U1-Pad3)")
+    (add_net "Net-(U1-Pad4)")
+    (add_net "Net-(U1-Pad5)")
+    (add_net "Net-(U1-Pad6)")
+  )
+
+  (module Package_DIP:DIP-16_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5EAC2E1C)
+    (at 48.768 31.623 270)
+    (descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
+    (tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
+    (path /5E9F2D6B)
+    (fp_text reference U1 (at 3.81 0.381 270) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 74HC595 (at 3.683 14.351) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.1 -1.55) (end -1.1 19.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.1 19.3) (end 8.7 19.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 8.7 19.3) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 3.556 9.398) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 13 "Net-(U1-Pad1)"))
+    (pad 9 thru_hole oval (at 7.62 17.78 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 12 /SOUT))
+    (pad 2 thru_hole oval (at 0 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 14 "Net-(U1-Pad2)"))
+    (pad 10 thru_hole oval (at 7.62 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 /VCC))
+    (pad 3 thru_hole oval (at 0 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 15 "Net-(U1-Pad3)"))
+    (pad 11 thru_hole oval (at 7.62 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 /SCLK))
+    (pad 4 thru_hole oval (at 0 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 16 "Net-(U1-Pad4)"))
+    (pad 12 thru_hole oval (at 7.62 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 /SCLK))
+    (pad 5 thru_hole oval (at 0 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 17 "Net-(U1-Pad5)"))
+    (pad 13 thru_hole oval (at 7.62 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 /GND))
+    (pad 6 thru_hole oval (at 0 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 18 "Net-(U1-Pad6)"))
+    (pad 14 thru_hole oval (at 7.62 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 11 /SIN))
+    (pad 7 thru_hole oval (at 0 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 15 thru_hole oval (at 7.62 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 19 "Net-(U1-Pad15)"))
+    (pad 8 thru_hole oval (at 0 17.78 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 /GND))
+    (pad 16 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 /VCC))
+    (model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_SO:SOIC-16_3.9x9.9mm_P1.27mm (layer F.Cu) (tedit 5E9F3989) (tstamp 5EAC28C6)
+    (at 24.257 33.782 180)
+    (descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
+    (tags "SOIC 1.27")
+    (path /5E9F2F28)
+    (attr smd)
+    (fp_text reference U2 (at 0 -3.429 180) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value ULN2003 (at 0.889 1.016 270) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at -0.635 -0.254 270) (layer F.Fab)
+      (effects (font (size 0.9 0.9) (thickness 0.135)))
+    )
+    (fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15))
+    (fp_line (start 1.95 -4.95) (end 1.95 4.95) (layer F.Fab) (width 0.15))
+    (fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15))
+    (fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15))
+    (fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15))
+    (fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.7 -5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.7 -5.25) (end 3.7 -5.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -3.7 5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -2.075 -5.075) (end -2.075 -5.05) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.075 -5.075) (end 2.075 -4.97) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.075 5.075) (end 2.075 4.97) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.075 5.075) (end -2.075 4.97) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.075 -5.075) (end 2.075 -5.075) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.075 5.075) (end 2.075 5.075) (layer F.SilkS) (width 0.15))
+    (fp_line (start -2.075 -5.05) (end -3.45 -5.05) (layer F.SilkS) (width 0.15))
+    (pad 1 smd rect (at -2.7 -4.445 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 19 "Net-(U1-Pad15)"))
+    (pad 2 smd rect (at -2.7 -3.175 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 13 "Net-(U1-Pad1)"))
+    (pad 3 smd rect (at -2.7 -1.905 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 14 "Net-(U1-Pad2)"))
+    (pad 4 smd rect (at -2.7 -0.635 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 15 "Net-(U1-Pad3)"))
+    (pad 5 smd rect (at -2.7 0.635 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 16 "Net-(U1-Pad4)"))
+    (pad 6 smd rect (at -2.7 1.905 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 17 "Net-(U1-Pad5)"))
+    (pad 7 smd rect (at -2.7 3.175 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 18 "Net-(U1-Pad6)"))
+    (pad 8 smd rect (at -2.7 4.445 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 10 /GND))
+    (pad 9 smd rect (at 2.7 4.445 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask))
+    (pad 10 smd rect (at 2.7 3.175 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 4 /S7))
+    (pad 11 smd rect (at 2.7 1.905 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 9 /S6))
+    (pad 12 smd rect (at 2.7 0.635 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 3 /S5))
+    (pad 13 smd rect (at 2.7 -0.635 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 8 /S4))
+    (pad 14 smd rect (at 2.7 -1.905 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 2 /S3))
+    (pad 15 smd rect (at 2.7 -3.175 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 7 /S2))
+    (pad 16 smd rect (at 2.7 -4.445 180) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
+      (net 1 /S1))
+    (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-16_3.9x9.9mm_P1.27mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module conn_te_micromatch:TE_MicroMatch_215750-0016_2x08_P1.27mm_Vertical (layer F.Cu) (tedit 5E9F481C) (tstamp 5ECA3085)
+    (at 22.098 44.577 90)
+    (descr "TE Connectivity MicroMatch")
+    (tags "connector AMP TE MicroMatch side entry")
+    (path /5E9F30D8)
+    (fp_text reference J1 (at -0.635 -1.905 270) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x12_Male (at -2.54 8.89 180) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -1.48 -1.27) (end 3.52 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.61 -1.38) (end 3.65 -1.38) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.52 -1.27) (end 3.52 20.3) (layer F.Fab) (width 0.1))
+    (fp_line (start 3.65 -1.38) (end 3.65 20.41) (layer F.SilkS) (width 0.12))
+    (fp_line (start 3.52 20.3) (end -1.48 20.3) (layer F.Fab) (width 0.1))
+    (fp_line (start 3.65 20.41) (end -1.61 20.41) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.48 -1.27) (end -1.48 -0.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.48 -0.5) (end -0.98 0) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.98 0) (end -1.48 0.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.48 0.5) (end -1.48 20.3) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.61 -1.38) (end -1.61 20.4) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.145 0) (end 1.745 0.3) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.745 0.3) (end 1.745 -0.3) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.745 -0.3) (end 1.145 0) (layer F.SilkS) (width 0.12))
+    (fp_text user %R (at -0.635 -1.905 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole roundrect (at 0 0 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask) (roundrect_rratio 0.192308)
+      (net 1 /S1))
+    (pad 3 thru_hole oval (at 0 2.54 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 /S3))
+    (pad 5 thru_hole oval (at 0 5.08 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 /S5))
+    (pad 7 thru_hole oval (at 0 7.62 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 /S7))
+    (pad 9 thru_hole oval (at 0 10.16 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 12 /SOUT))
+    (pad 11 thru_hole oval (at 0 12.7 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 /SCLK))
+    (pad 13 thru_hole oval (at 0 15.24 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 15 thru_hole oval (at 0 17.78 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 2 thru_hole oval (at 2.54 1.27 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 /S2))
+    (pad 4 thru_hole oval (at 2.54 3.81 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 8 /S4))
+    (pad 6 thru_hole oval (at 2.54 6.35 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 9 /S6))
+    (pad 8 thru_hole oval (at 2.54 8.89 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 /GND))
+    (pad 10 thru_hole oval (at 2.54 11.43 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 /VCC))
+    (pad 12 thru_hole oval (at 2.54 13.97 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask)
+      (net 11 /SIN))
+    (pad 14 thru_hole oval (at 2.54 16.51 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 16 thru_hole oval (at 2.54 19.05 90) (size 1.8 1.3) (drill 0.8) (layers *.Cu *.Mask))
+    (pad "" np_thru_hole circle (at 1.8 -1.4 90) (size 1.5 1.5) (drill 1.5) (layers *.Cu *.Mask))
+    (model ${KISYS3DMOD}/Connector_Molex.3dshapes/Molex_Picoflex_90325-0016_2x08_P1.27mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (dimension 31.369 (width 0.3) (layer Cmts.User)
+    (gr_text "31,369 mm" (at 35.1155 23.681) (layer Cmts.User)
+      (effects (font (size 1.5 1.5) (thickness 0.3)))
+    )
+    (feature1 (pts (xy 50.8 27.94) (xy 50.8 25.194579)))
+    (feature2 (pts (xy 19.431 27.94) (xy 19.431 25.194579)))
+    (crossbar (pts (xy 19.431 25.781) (xy 50.8 25.781)))
+    (arrow1a (pts (xy 50.8 25.781) (xy 49.673496 26.367421)))
+    (arrow1b (pts (xy 50.8 25.781) (xy 49.673496 25.194579)))
+    (arrow2a (pts (xy 19.431 25.781) (xy 20.557504 26.367421)))
+    (arrow2b (pts (xy 19.431 25.781) (xy 20.557504 25.194579)))
+  )
+  (gr_line (start 23.368 40.513) (end 23.368 37.592) (layer B.SilkS) (width 0.2))
+  (gr_line (start 22.098 43.307) (end 22.098 37.592) (layer B.SilkS) (width 0.2))
+  (gr_line (start 27.178 43.307) (end 27.178 37.592) (layer B.SilkS) (width 0.2))
+  (dimension 18.542 (width 0.3) (layer Cmts.User)
+    (gr_text "18,542 mm" (at 14.537 37.211 270) (layer Cmts.User)
+      (effects (font (size 1.5 1.5) (thickness 0.3)))
+    )
+    (feature1 (pts (xy 20.066 46.482) (xy 16.050579 46.482)))
+    (feature2 (pts (xy 20.066 27.94) (xy 16.050579 27.94)))
+    (crossbar (pts (xy 16.637 27.94) (xy 16.637 46.482)))
+    (arrow1a (pts (xy 16.637 46.482) (xy 16.050579 45.355496)))
+    (arrow1b (pts (xy 16.637 46.482) (xy 17.223421 45.355496)))
+    (arrow2a (pts (xy 16.637 27.94) (xy 16.050579 29.066504)))
+    (arrow2b (pts (xy 16.637 27.94) (xy 17.223421 29.066504)))
+  )
+  (gr_line (start 34.798 43.307) (end 34.798 38.354) (layer B.SilkS) (width 0.2))
+  (gr_line (start 32.258 43.307) (end 32.258 38.354) (layer B.SilkS) (width 0.2))
+  (gr_line (start 29.718 43.307) (end 29.718 37.592) (layer B.SilkS) (width 0.2))
+  (gr_line (start 28.448 40.513) (end 28.448 37.592) (layer B.SilkS) (width 0.2))
+  (gr_line (start 25.908 40.513) (end 25.908 37.592) (layer B.SilkS) (width 0.2))
+  (gr_line (start 24.638 37.592) (end 24.638 43.307) (layer B.SilkS) (width 0.2))
+  (gr_text "S1\nS2\nS3\nS4\nS5\nS6\nS7\nGND\nSOUT\nVCC\nSCLK\nSIN" (at 29.083 36.576 90) (layer B.SilkS)
+    (effects (font (size 0.73 0.8) (thickness 0.175)) (justify mirror))
+  )
+  (gr_line (start 19.431 46.482) (end 50.8 46.482) (layer Edge.Cuts) (width 0.15))
+  (gr_line (start 19.431 27.94) (end 19.431 46.482) (layer Edge.Cuts) (width 0.15))
+  (gr_line (start 50.8 27.94) (end 19.431 27.94) (layer Edge.Cuts) (width 0.15))
+  (gr_line (start 50.8 46.482) (end 50.8 27.94) (layer Edge.Cuts) (width 0.15))
+
+  (segment (start 22.098 44.577) (end 22.098 41.562) (width 0.25) (layer F.Cu) (net 1))
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+  (segment (start 29.718 41.275) (end 29.718 44.577) (width 0.25) (layer F.Cu) (net 4))
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+  (segment (start 46.228 32.893) (end 46.228 31.623) (width 0.25) (layer F.Cu) (net 14))
+  (segment (start 43.434 35.687) (end 46.228 32.893) (width 0.25) (layer F.Cu) (net 14))
+  (segment (start 26.957 35.687) (end 43.434 35.687) (width 0.25) (layer F.Cu) (net 14))
+  (segment (start 26.957 34.417) (end 27.432 34.417) (width 0.25) (layer F.Cu) (net 15))
+  (segment (start 43.688 32.893) (end 43.688 31.623) (width 0.25) (layer F.Cu) (net 15))
+  (segment (start 42.164 34.417) (end 43.688 32.893) (width 0.25) (layer F.Cu) (net 15))
+  (segment (start 26.957 34.417) (end 42.164 34.417) (width 0.25) (layer F.Cu) (net 15))
+  (segment (start 41.148 32.75437) (end 41.148 31.623) (width 0.25) (layer F.Cu) (net 16))
+  (segment (start 41.148 32.893) (end 41.148 32.75437) (width 0.25) (layer F.Cu) (net 16))
+  (segment (start 40.276 33.765) (end 41.148 32.893) (width 0.25) (layer F.Cu) (net 16))
+  (segment (start 28.575 33.765) (end 40.276 33.765) (width 0.25) (layer F.Cu) (net 16))
+  (segment (start 26.957 33.147) (end 27.957 33.147) (width 0.25) (layer F.Cu) (net 16))
+  (segment (start 27.957 33.147) (end 28.575 33.765) (width 0.25) (layer F.Cu) (net 16))
+  (segment (start 26.957 31.877) (end 27.407 31.877) (width 0.25) (layer F.Cu) (net 17))
+  (segment (start 38.608 32.893) (end 38.608 31.623) (width 0.25) (layer F.Cu) (net 17))
+  (segment (start 38.227 33.274) (end 38.608 32.893) (width 0.25) (layer F.Cu) (net 17))
+  (segment (start 29.354 33.274) (end 38.227 33.274) (width 0.25) (layer F.Cu) (net 17))
+  (segment (start 27.957 31.877) (end 29.354 33.274) (width 0.25) (layer F.Cu) (net 17))
+  (segment (start 26.957 31.877) (end 27.957 31.877) (width 0.25) (layer F.Cu) (net 17))
+  (segment (start 26.957 30.607) (end 27.407 30.607) (width 0.25) (layer F.Cu) (net 18))
+  (segment (start 27.957 30.607) (end 26.957 30.607) (width 0.25) (layer F.Cu) (net 18))
+  (segment (start 35.577999 32.748001) (end 30.098001 32.748001) (width 0.25) (layer F.Cu) (net 18))
+  (segment (start 30.098001 32.748001) (end 27.957 30.607) (width 0.25) (layer F.Cu) (net 18))
+  (segment (start 36.068 32.258) (end 35.577999 32.748001) (width 0.25) (layer F.Cu) (net 18))
+  (segment (start 36.068 31.623) (end 36.068 32.258) (width 0.25) (layer F.Cu) (net 18))
+  (segment (start 26.957 38.227) (end 27.407 38.227) (width 0.25) (layer F.Cu) (net 19))
+  (segment (start 27.957 38.227) (end 26.957 38.227) (width 0.25) (layer F.Cu) (net 19))
+  (segment (start 29.227 36.957) (end 27.957 38.227) (width 0.25) (layer F.Cu) (net 19))
+  (segment (start 45.212 36.957) (end 29.227 36.957) (width 0.25) (layer F.Cu) (net 19))
+  (segment (start 46.228 37.973) (end 45.212 36.957) (width 0.25) (layer F.Cu) (net 19))
+  (segment (start 46.228 39.243) (end 46.228 37.973) (width 0.25) (layer F.Cu) (net 19))
+
+)
Index: ledclock/circuit/ledclock/ledclock.net
===================================================================
--- ledclock/circuit/ledclock/ledclock.net	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
+++ ledclock/circuit/ledclock/ledclock.net	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
@@ -0,0 +1,200 @@
+(export (version D)
+  (design
+    (source /home/adestugues/opensource/avrstuff/ledclock/circuit/ledclock/ledclock.sch)
+    (date "mar. 21 avril 2020 21:24:21 CEST")
+    (tool "Eeschema 5.0.2+dfsg1-1")
+    (sheet (number 1) (name /) (tstamps /)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source ledclock.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value "")))))
+  (components
+    (comp (ref U1)
+      (value 74HC595)
+      (footprint Package_DIP:DIP-16_W7.62mm)
+      (datasheet http://www.ti.com/lit/ds/symlink/sn74hc595.pdf)
+      (libsource (lib 74xx) (part 74HC595) (description "8-bit serial in/out Shift Register 3-State Outputs"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5E9F2D6B))
+    (comp (ref U2)
+      (value ULN2003)
+      (footprint Package_SO:SOIC-16_3.9x9.9mm_P1.27mm)
+      (datasheet http://www.ti.com/lit/ds/symlink/uln2003a.pdf)
+      (libsource (lib Transistor_Array) (part ULN2003) (description "High Voltage, High Current Darlington Transistor Arrays, SOIC16/SOIC16W/DIP16/TSSOP16"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5E9F2F28))
+    (comp (ref J1)
+      (value Conn_01x12_Male)
+      (footprint conn_te_micromatch:TE_MicroMatch_215750-0016_2x08_P1.27mm_Vertical)
+      (datasheet ~)
+      (libsource (lib Connector) (part Conn_01x12_Male) (description "Generic connector, single row, 01x12, script generated (kicad-library-utils/schlib/autogen/connector/)"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5E9F30D8)))
+  (libparts
+    (libpart (lib 74xx) (part 74HC595)
+      (aliases
+        (alias 74LS595)
+        (alias 74HCT595))
+      (description "8-bit serial in/out Shift Register 3-State Outputs")
+      (docs http://www.ti.com/lit/ds/symlink/sn74hc595.pdf)
+      (footprints
+        (fp DIP*W7.62mm*)
+        (fp SOIC*3.9x9.9mm*P1.27mm*)
+        (fp TSSOP*4.4x5mm*P0.65mm*)
+        (fp SOIC*5.3x10.2mm*P1.27mm*)
+        (fp SOIC*7.5x10.3mm*P1.27mm*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) 74HC595))
+      (pins
+        (pin (num 1) (name QB) (type 3state))
+        (pin (num 2) (name QC) (type 3state))
+        (pin (num 3) (name QD) (type 3state))
+        (pin (num 4) (name QE) (type 3state))
+        (pin (num 5) (name QF) (type 3state))
+        (pin (num 6) (name QG) (type 3state))
+        (pin (num 7) (name QH) (type 3state))
+        (pin (num 8) (name GND) (type power_in))
+        (pin (num 9) (name QH') (type output))
+        (pin (num 10) (name ~SRCLR) (type input))
+        (pin (num 11) (name SRCLK) (type input))
+        (pin (num 12) (name RCLK) (type input))
+        (pin (num 13) (name ~OE) (type input))
+        (pin (num 14) (name SER) (type input))
+        (pin (num 15) (name QA) (type 3state))
+        (pin (num 16) (name VCC) (type power_in))))
+    (libpart (lib Connector) (part Conn_01x12_Male)
+      (description "Generic connector, single row, 01x12, script generated (kicad-library-utils/schlib/autogen/connector/)")
+      (docs ~)
+      (footprints
+        (fp Connector*:*_1x??_*))
+      (fields
+        (field (name Reference) J)
+        (field (name Value) Conn_01x12_Male))
+      (pins
+        (pin (num 1) (name Pin_1) (type passive))
+        (pin (num 2) (name Pin_2) (type passive))
+        (pin (num 3) (name Pin_3) (type passive))
+        (pin (num 4) (name Pin_4) (type passive))
+        (pin (num 5) (name Pin_5) (type passive))
+        (pin (num 6) (name Pin_6) (type passive))
+        (pin (num 7) (name Pin_7) (type passive))
+        (pin (num 8) (name Pin_8) (type passive))
+        (pin (num 9) (name Pin_9) (type passive))
+        (pin (num 10) (name Pin_10) (type passive))
+        (pin (num 11) (name Pin_11) (type passive))
+        (pin (num 12) (name Pin_12) (type passive))))
+    (libpart (lib Transistor_Array) (part ULN2003)
+      (aliases
+        (alias ULN2003A)
+        (alias ULN2002)
+        (alias ULN2002A)
+        (alias ULN2004)
+        (alias ULN2004A))
+      (description "High Voltage, High Current Darlington Transistor Arrays, SOIC16/SOIC16W/DIP16/TSSOP16")
+      (docs http://www.ti.com/lit/ds/symlink/uln2003a.pdf)
+      (footprints
+        (fp DIP*W7.62mm*)
+        (fp SOIC*3.9x9.9mm*P1.27mm*)
+        (fp SSOP*4.4x5.2mm*P0.65mm*)
+        (fp TSSOP*4.4x5mm*P0.65mm*)
+        (fp SOIC*W*5.3x10.2mm*P1.27mm*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) ULN2003))
+      (pins
+        (pin (num 1) (name I1) (type input))
+        (pin (num 2) (name I2) (type input))
+        (pin (num 3) (name I3) (type input))
+        (pin (num 4) (name I4) (type input))
+        (pin (num 5) (name I5) (type input))
+        (pin (num 6) (name I6) (type input))
+        (pin (num 7) (name I7) (type input))
+        (pin (num 8) (name GND) (type power_in))
+        (pin (num 9) (name COM) (type passive))
+        (pin (num 10) (name O7) (type openCol))
+        (pin (num 11) (name O6) (type openCol))
+        (pin (num 12) (name O5) (type openCol))
+        (pin (num 13) (name O4) (type openCol))
+        (pin (num 14) (name O3) (type openCol))
+        (pin (num 15) (name O2) (type openCol))
+        (pin (num 16) (name O1) (type openCol)))))
+  (libraries
+    (library (logical 74xx)
+      (uri /usr/share/kicad/library/74xx.lib))
+    (library (logical Connector)
+      (uri /usr/share/kicad/library/Connector.lib))
+    (library (logical Transistor_Array)
+      (uri /usr/share/kicad/library/Transistor_Array.lib)))
+  (nets
+    (net (code 1) (name "Net-(U1-Pad7)")
+      (node (ref U1) (pin 7)))
+    (net (code 2) (name /VCC)
+      (node (ref U1) (pin 16))
+      (node (ref U1) (pin 10))
+      (node (ref J1) (pin 10)))
+    (net (code 3) (name /GND)
+      (node (ref U1) (pin 13))
+      (node (ref U1) (pin 8))
+      (node (ref J1) (pin 8))
+      (node (ref U2) (pin 8)))
+    (net (code 4) (name /SOUT)
+      (node (ref J1) (pin 9))
+      (node (ref U1) (pin 9)))
+    (net (code 5) (name /S7)
+      (node (ref U2) (pin 10))
+      (node (ref J1) (pin 7)))
+    (net (code 6) (name /S6)
+      (node (ref J1) (pin 6))
+      (node (ref U2) (pin 11)))
+    (net (code 7) (name "Net-(U2-Pad9)")
+      (node (ref U2) (pin 9)))
+    (net (code 8) (name /S5)
+      (node (ref U2) (pin 12))
+      (node (ref J1) (pin 5)))
+    (net (code 9) (name "Net-(U1-Pad5)")
+      (node (ref U2) (pin 6))
+      (node (ref U1) (pin 5)))
+    (net (code 10) (name "Net-(U1-Pad6)")
+      (node (ref U2) (pin 7))
+      (node (ref U1) (pin 6)))
+    (net (code 11) (name "Net-(U1-Pad4)")
+      (node (ref U2) (pin 5))
+      (node (ref U1) (pin 4)))
+    (net (code 12) (name "Net-(U1-Pad3)")
+      (node (ref U1) (pin 3))
+      (node (ref U2) (pin 4)))
+    (net (code 13) (name "Net-(U1-Pad2)")
+      (node (ref U1) (pin 2))
+      (node (ref U2) (pin 3)))
+    (net (code 14) (name "Net-(U1-Pad15)")
+      (node (ref U1) (pin 15))
+      (node (ref U2) (pin 1)))
+    (net (code 15) (name /S4)
+      (node (ref J1) (pin 4))
+      (node (ref U2) (pin 13)))
+    (net (code 16) (name /S3)
+      (node (ref U2) (pin 14))
+      (node (ref J1) (pin 3)))
+    (net (code 17) (name /S2)
+      (node (ref U2) (pin 15))
+      (node (ref J1) (pin 2)))
+    (net (code 18) (name /SIN)
+      (node (ref J1) (pin 12))
+      (node (ref U1) (pin 14)))
+    (net (code 19) (name /SCLK)
+      (node (ref J1) (pin 11))
+      (node (ref U1) (pin 11))
+      (node (ref U1) (pin 12)))
+    (net (code 20) (name /S1)
+      (node (ref J1) (pin 1))
+      (node (ref U2) (pin 16)))
+    (net (code 21) (name "Net-(U1-Pad1)")
+      (node (ref U1) (pin 1))
+      (node (ref U2) (pin 2)))))
Index: ledclock/circuit/ledclock/ledclock.pro
===================================================================
--- ledclock/circuit/ledclock/ledclock.pro	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
+++ ledclock/circuit/ledclock/ledclock.pro	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
Index: ledclock/circuit/ledclock/ledclock.sch
===================================================================
--- ledclock/circuit/ledclock/ledclock.sch	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
+++ ledclock/circuit/ledclock/ledclock.sch	(revision 8f204fcec408b9dc6043ffe2b1ed20d525c43d10)
@@ -0,0 +1,141 @@
+EESchema Schematic File Version 4
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 74xx:74HC595 U1
+U 1 1 5E9F2D6B
+P 2550 2800
+F 0 "U1" H 2650 3500 50  0000 C CNN
+F 1 "74HC595" H 2750 3400 50  0000 C CNN
+F 2 "Package_DIP:DIP-16_W7.62mm" H 2550 2800 50  0001 C CNN
+F 3 "http://www.ti.com/lit/ds/symlink/sn74hc595.pdf" H 2550 2800 50  0001 C CNN
+	1    2550 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L Transistor_Array:ULN2003 U2
+U 1 1 5E9F2F28
+P 3800 2600
+F 0 "U2" H 3800 3267 50  0000 C CNN
+F 1 "ULN2003" H 3800 3176 50  0000 C CNN
+F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 3850 2050 50  0001 L CNN
+F 3 "http://www.ti.com/lit/ds/symlink/uln2003a.pdf" H 3900 2400 50  0001 C CNN
+	1    3800 2600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2950 2400 3400 2400
+Wire Wire Line
+	2950 2500 3400 2500
+Wire Wire Line
+	2950 2600 3400 2600
+Wire Wire Line
+	2950 2700 3400 2700
+Wire Wire Line
+	2950 2800 3400 2800
+Wire Wire Line
+	2950 2900 3400 2900
+Wire Wire Line
+	2950 3000 3400 3000
+$Comp
+L Connector:Conn_01x12_Male J1
+U 1 1 5E9F30D8
+P 800 2950
+F 0 "J1" H 906 3628 50  0000 C CNN
+F 1 "Conn_01x12_Male" H 906 3537 50  0000 C CNN
+F 2 "conn_te_micromatch:TE_MicroMatch_215750-0016_2x08_P1.27mm_Vertical" H 800 2950 50  0001 C CNN
+F 3 "~" H 800 2950 50  0001 C CNN
+	1    800  2950
+	1    0    0    -1  
+$EndComp
+Text Label 1000 2450 0    50   ~ 0
+S1
+Text Label 1000 2550 0    50   ~ 0
+S2
+Text Label 1000 2650 0    50   ~ 0
+S3
+Text Label 1000 2750 0    50   ~ 0
+S4
+Text Label 1000 2850 0    50   ~ 0
+S5
+Text Label 1000 2950 0    50   ~ 0
+S6
+Text Label 1000 3050 0    50   ~ 0
+S7
+Text Label 1000 3150 0    50   ~ 0
+GND
+Text Label 1000 3350 0    50   ~ 0
+VCC
+Text Label 1000 3550 0    50   ~ 0
+SIN
+Text Label 1000 3450 0    50   ~ 0
+SCLK
+Text Label 1000 3250 0    50   ~ 0
+SOUT
+Wire Wire Line
+	2550 3500 3800 3500
+Wire Wire Line
+	3800 3500 3800 3200
+Text Label 3150 3500 0    50   ~ 0
+GND
+Wire Wire Line
+	2550 2200 2550 2000
+Text Label 2550 1650 0    50   ~ 0
+VCC
+NoConn ~ 2950 3100
+Text Label 2950 3300 0    50   ~ 0
+SOUT
+Wire Wire Line
+	2150 2700 1750 2700
+Wire Wire Line
+	1750 2700 1750 2000
+Wire Wire Line
+	1750 2000 2550 2000
+Connection ~ 2550 2000
+Wire Wire Line
+	2550 2000 2550 1650
+Text Label 1950 2600 0    50   ~ 0
+SCLK
+Wire Wire Line
+	1950 2600 2150 2600
+Wire Wire Line
+	1950 2400 2150 2400
+Text Label 1950 2400 0    50   ~ 0
+SIN
+Wire Wire Line
+	2150 3000 2150 3500
+Wire Wire Line
+	2150 3500 2550 3500
+Connection ~ 2550 3500
+Wire Wire Line
+	2150 2900 1950 2900
+Wire Wire Line
+	1950 2900 1950 2600
+Text Label 4200 2400 0    50   ~ 0
+S1
+Text Label 4200 2500 0    50   ~ 0
+S2
+Text Label 4200 2600 0    50   ~ 0
+S3
+Text Label 4200 2700 0    50   ~ 0
+S4
+Text Label 4200 2800 0    50   ~ 0
+S5
+Text Label 4200 2900 0    50   ~ 0
+S6
+Text Label 4200 3000 0    50   ~ 0
+S7
+NoConn ~ 4200 2200
+$EndSCHEMATC
