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====== The 6821 PIA ======
This is a generic I/O chip designed by Motorola and manufactured by Thomson as a second source. It is present in every Thomson machine.

===== Programming and architecture =====
==== Registers ====

The 6881 exposes 4 registers to the CPU. They are, in this order:
  * Data port A
  * Data port B
  * Control port A
  * Control port B

The control registers have the following functions:
=== Bit 7: interrput pin 1 state ===
This bit is set on transition (low>high or high>low) of the CA1 or CB1 pin. It is cleared by reading the output register.

=== Bit 6: interrput pin 2 state ===
This works the same as bit 7, but is only used when CA2 or CB2 is configured as an input pin. Otherwise, the pin can't be used as an interrupt source.

=== Bits 5-3: CA2/CB2 control ===
When bit 5 is 0, CA2/CB2 is set as an input pin, and can be used for interrupts.
In this case, the two other bits have the following meaning:
  * bit 4: set this bit to emit interrupts on rising edges of CA2/CB2. Clear it to emit interrupts on the falling edges.
  * bit 3: Enable IRQA/B generation for CA2. When interrupts are disabled, bit 6 can still be used to poll the state of CA2/CB2.

When bit 5 is 1, CA2/CB2 is set as an output pin.
  * bit 4 set: the value of bit 3 is written to the pin
  * bit 4 clear: peripheral extension mode enabled. Bit 3 selects CA1/CB1 restore or E restore.

=== Bit 2: data register configuration ===
Setting this bit to 0 maps the data register to "direction configuration". In this mode, writing to the data register allows configuring each bit as an output or input.

Setting it to 1 maps the output register instead, allowing to read and write the current level of the 8 bits on each port.

==== Peripheral expansion mode ====
In this mode, the PIA can be used to map other peripherals indirectly to the CPU bus. Pins CA2 and CB2 are used as read and write signal lines.
This allows communication with slow peripherals, with the following scheme:

  * CA2 mirrors the "READ" signal decoded by the PIA. It goes low when output register A is read, and then goes high again either when the PIA is de-selected ("E-restore"), or when CA1 triggers an interrupt ("CA1-restore").
  * CB2 mirrors the "WRITE" signal in a similar way. It goes low when output register B is written, and then goes high again either when the PIA is de-selected ("E-restore"), or when CB1 triggers an interrupt ("CB1-restore").

==== Interrupts ====
===== Uses =====
==== MO "System" PIA ====
=== data port A (A7C0) ===
  * bit 0: /FORME - Switch the screen RAM mapping between pixel and attribute RAMs
  * bits 1-4: border color (R,G,B,P)
  * bit 5: light pen button
  * bit 6: tape drive data output
  * bit 7: tape drive data input

Bit 7 is low when no tape drive is plugged, and high when there is one. The monitor loading and saving code checks for this to detect the tape drive.

=== data port B (A7C1) ===
  * bit 0: sound output
  * bits 1-3: keyboard column to scan
  * bits 4-6: keyboard line to scan
  * bit 7: state of key selected by the column and line

=== Control ports (A7C2, A7C3) ===
  * CA1: lightpen interrupt (IRQA is wired to 6809 FIRQ)
  * CA2: tape drive motor control (output)
  * CB1: 50Hz interrupt (IRQB is wired to 6809 IRQ)
  * CB2: video incrustation enable (output)

==== TO "System" PIA ====

=== Data port A (E7C8) ===

== PA0: KTEST ==
This bit is set by the keyboard system while a key is pressed. This allows the keyboard handler code to know if it needs to do a full keyboard scan.

== PA1-PA7: printer data bits ==
These bits are wired to printer port D1-D7. Bit 0 is PB0 (this would have been too simple!)

=== Data port B (E7C9) ===

== PB0-PB1: printer missing bits ==
  * PB0 is data bit 0
  * PB1 is /STROBE for the printer port.
== PB2: video incrustation control ==
set to 0 to enable video incrustation mode. Note this needs specific hardware for synchronizing the system clock to the external video.

== PB3-PB6: memory expansion control ==

These bits allows to map **some** of the expanded memory in TO machines.
When no internal RAM is selected (bits are all 1), an external expansion (on the TO9) may be used. This is controlled by [[documentations:devices:6846#p2_and_p6_ramdisk_expansion_control|bits P2 and P6]] of the 6846 PIA.

^P6^P2^PB7^PB6^PB5^PB4^PB3^Mapped memory at A000-DFFF      ^
^X ^X ^1  ^1  ^1  ^X  ^X  ^TO7 32K expansion mappings      ^
|X |X |1  |1  |1  |1  |0  |Internal bank 0                 |
|X |X |1  |1  |1  |0  |1  |Internal bank 1                 |
^X ^X ^X  ^X  ^0  ^1  ^1  ^TO9 extra internal RAM mappings ^
|X |X |0  |0  |0  |1  |1  |Internal bank 2                 |
|X |X |1  |0  |0  |1  |1  |Internal bank 3                 |
|X |X |0  |1  |0  |1  |1  |Internal bank 4                 |
|X |X |1  |1  |0  |1  |1  |Internal bank 5                 |
^X ^X ^1  ^1  ^1  ^1  ^1  ^TO9 external RAM mappings       ^
|0 |0 |1  |1  |1  |1  |1  |RAMdisk 1                       |
|1 |0 |1  |1  |1  |1  |1  |RAMdisk 2                       |
|0 |1 |1  |1  |1  |1  |1  |RAMdisk 3                       |
|1 |1 |1  |1  |1  |1  |1  |RAMdisk 4                       |

And to add to the fun: instead of simply programming the registers to 0 or 1 using the data port, you must program them as inputs (for 1) or outputs (for 0). The data register is always at 0. the idea is to allow the other bits (0-2 and 7) to be used safely, without risking to enable two RAM banks at the same time.

Seriously, this system is a mess. Use the new banking from the gate array if you can.

=== Control port A (E7CA) ===
== CA1: video incrustation sync ==
This is connected to the video incrustation CLRG signal. The only use is detecting that the signal is available from software. This is useful, because switching the video incrustation on without this would crash the machine.

== CA2: Tape drive motor control ==
Active low.

== CB1: Lightpen FIRQ ==
Triggered when the lightpen sensor detects the screen refresh.

=== Control port B (E7CB) ===
==== "Sound and Games" PIA ====

Available as an expansion for the TO7, TO7/70, TO9 and MO5, this is built-in for the other machines.

<columns>

=== Data port A (x7CC) ===
^Bit^Joystick 0 ^Mouse       ^Joystick 1^
|PA0|Up         |Left click  | |
|PA1|Down       |Right click | |
|PA2|Left       |XB          | |
|PA3|Right      |YB          | |
|PA4| | |Up   |
|PA5| | |Down |
|PA6| | |Left |
|PA7| | |Right|

<newcolumn>

=== Data port B (x7CD) ===

^Bit^Joysticks      ^Mouse^Sound    ^
|PB0|Common 0       |     |DAC bit 0|
|PB1|Common 1       |     |DAC bit 1|
|PB2|Joy0 button 2  |XA   |DAC bit 2|
|PB3|Joy1 button 2  |     |DAC bit 3|
|PB4| | |DAC bit 4|
|PB5| | |DAC bit 5|   
|PB6|Joy0 button 1  |YA | |
|PB7|Joy1 button 1  | | |

</columns>

=== Control ports (x7CE/x7CF) ===
The joystick buttons are wired both to port input pins and to control pins. This makes it possible to trigger interrupts on them, but read the complete joystick state for both joysticks on data ports A and B without having to also test the control ports.
  * CA1: Joy0 button 2
  * CA2: Joy0 button 1
  * CB1: Joy1 button 2
  * CB2: Joy1 button 1

It is not possible to use the DAC and the joysticks (or the mouse) at the same time! This is particularly annoying for the mouse, as one of the quadrature encoded signals will interfere with the DAC. So you have to move the mouse very slowly until it is not interfering anymore. Or, you can unplug the mouse when it is not in use.

The sound output from the DAC can be muted by using the 6846 buzzer output to force it low. Or, the DAC cn be used as a "volume control" for the buzzer, because of the way they are mixed together.

===== Documents =====
  * {{:documentations:devices:pia_6821.pdf|Datasheet}}