| 1 | ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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| 2 | ;***** Created: 2005-01-11 10:30 ******* Source: AT90S2313.xml ***********
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| 3 | ;*************************************************************************
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| 4 | ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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| 5 | ;*
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| 6 | ;* Number : AVR000
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| 7 | ;* File Name : "2313def.inc"
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| 8 | ;* Title : Register/Bit Definitions for the AT90S2313
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| 9 | ;* Date : 2005-01-11
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| 10 | ;* Version : 2.14
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| 11 | ;* Support E-mail : avr@atmel.com
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| 12 | ;* Target MCU : AT90S2313
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| 13 | ;*
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| 14 | ;* DESCRIPTION
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| 15 | ;* When including this file in the assembly program file, all I/O register
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| 16 | ;* names and I/O register bit names appearing in the data book can be used.
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| 17 | ;* In addition, the six registers forming the three data pointers X, Y and
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| 18 | ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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| 19 | ;* SRAM is also defined
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| 20 | ;*
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| 21 | ;* The Register names are represented by their hexadecimal address.
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| 22 | ;*
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| 23 | ;* The Register Bit names are represented by their bit number (0-7).
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| 24 | ;*
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| 25 | ;* Please observe the difference in using the bit names with instructions
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| 26 | ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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| 27 | ;* (skip if bit in register set/cleared). The following example illustrates
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| 28 | ;* this:
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| 29 | ;*
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| 30 | ;* in r16,PORTB ;read PORTB latch
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| 31 | ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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| 32 | ;* out PORTB,r16 ;output to PORTB
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| 33 | ;*
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| 34 | ;* in r16,TIFR ;read the Timer Interrupt Flag Register
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| 35 | ;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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| 36 | ;* rjmp TOV0_is_set ;jump if set
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| 37 | ;* ... ;otherwise do something else
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| 38 | ;*************************************************************************
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| 39 |
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| 40 | #ifndef _2313DEF_INC_
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| 41 | #define _2313DEF_INC_
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| 42 |
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| 43 |
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| 44 | #pragma partinc 0
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| 45 |
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| 46 | ; ***** SPECIFY DEVICE ***************************************************
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| 47 | .device AT90S2313
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| 48 | #pragma AVRPART ADMIN PART_NAME AT90S2313
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| 49 | .equ SIGNATURE_000 = 0x1e
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| 50 | .equ SIGNATURE_001 = 0x91
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| 51 | .equ SIGNATURE_002 = 0x01
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| 52 |
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| 53 | #pragma AVRPART CORE CORE_VERSION V1
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| 54 |
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| 55 |
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| 56 | ; ***** I/O REGISTER DEFINITIONS *****************************************
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| 57 | ; NOTE:
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| 58 | ; Definitions marked "MEMORY MAPPED"are extended I/O ports
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| 59 | ; and cannot be used with IN/OUT instructions
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| 60 | .equ SREG = 0x3f
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| 61 | .equ SPL = 0x3d
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| 62 | .equ GIMSK = 0x3b
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| 63 | .equ GIFR = 0x3a
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| 64 | .equ TIMSK = 0x39
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| 65 | .equ TIFR = 0x38
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| 66 | .equ MCUCR = 0x35
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| 67 | .equ TCCR0 = 0x33
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| 68 | .equ TCNT0 = 0x32
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| 69 | .equ TCCR1A = 0x2f
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| 70 | .equ TCCR1B = 0x2e
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| 71 | .equ TCNT1H = 0x2d
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| 72 | .equ TCNT1L = 0x2c
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| 73 | .equ OCR1AH = 0x2b
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| 74 | .equ OCR1AL = 0x2a
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| 75 | .equ ICR1H = 0x25
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| 76 | .equ ICR1L = 0x24
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| 77 | .equ WDTCR = 0x21
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| 78 | .equ EEAR = 0x1e
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| 79 | .equ EEDR = 0x1d
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| 80 | .equ EECR = 0x1c
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| 81 | .equ PORTB = 0x18
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| 82 | .equ DDRB = 0x17
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| 83 | .equ PINB = 0x16
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| 84 | .equ PORTD = 0x12
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| 85 | .equ DDRD = 0x11
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| 86 | .equ PIND = 0x10
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| 87 | .equ UDR = 0x0c
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| 88 | .equ USR = 0x0b
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| 89 | .equ UCR = 0x0a
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| 90 | .equ UBRR = 0x09
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| 91 | .equ ACSR = 0x08
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| 92 |
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| 93 |
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| 94 | ; ***** BIT DEFINITIONS **************************************************
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| 95 |
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| 96 | ; ***** PORTB ************************
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| 97 | ; PORTB - Port B Data Register
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| 98 | .equ PORTB0 = 0 ; Port B Data Register bit 0
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| 99 | .equ PB0 = 0 ; For compatibility
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| 100 | .equ PORTB1 = 1 ; Port B Data Register bit 1
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| 101 | .equ PB1 = 1 ; For compatibility
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| 102 | .equ PORTB2 = 2 ; Port B Data Register bit 2
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| 103 | .equ PB2 = 2 ; For compatibility
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| 104 | .equ PORTB3 = 3 ; Port B Data Register bit 3
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| 105 | .equ PB3 = 3 ; For compatibility
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| 106 | .equ PORTB4 = 4 ; Port B Data Register bit 4
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| 107 | .equ PB4 = 4 ; For compatibility
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| 108 | .equ PORTB5 = 5 ; Port B Data Register bit 5
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| 109 | .equ PB5 = 5 ; For compatibility
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| 110 | .equ PORTB6 = 6 ; Port B Data Register bit 6
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| 111 | .equ PB6 = 6 ; For compatibility
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| 112 | .equ PORTB7 = 7 ; Port B Data Register bit 7
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| 113 | .equ PB7 = 7 ; For compatibility
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| 114 |
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| 115 | ; DDRB - Port B Data Direction Register
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| 116 | .equ DDB0 = 0 ; Port B Data Direction Register bit 0
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| 117 | .equ DDB1 = 1 ; Port B Data Direction Register bit 1
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| 118 | .equ DDB2 = 2 ; Port B Data Direction Register bit 2
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| 119 | .equ DDB3 = 3 ; Port B Data Direction Register bit 3
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| 120 | .equ DDB4 = 4 ; Port B Data Direction Register bit 4
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| 121 | .equ DDB5 = 5 ; Port B Data Direction Register bit 5
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| 122 | .equ DDB6 = 6 ; Port B Data Direction Register bit 6
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| 123 | .equ DDB7 = 7 ; Port B Data Direction Register bit 7
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| 124 |
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| 125 | ; PINB - Port B Input Pins
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| 126 | .equ PINB0 = 0 ; Port B Input Pins bit 0
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| 127 | .equ PINB1 = 1 ; Port B Input Pins bit 1
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| 128 | .equ PINB2 = 2 ; Port B Input Pins bit 2
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| 129 | .equ PINB3 = 3 ; Port B Input Pins bit 3
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| 130 | .equ PINB4 = 4 ; Port B Input Pins bit 4
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| 131 | .equ PINB5 = 5 ; Port B Input Pins bit 5
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| 132 | .equ PINB6 = 6 ; Port B Input Pins bit 6
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| 133 | .equ PINB7 = 7 ; Port B Input Pins bit 7
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| 134 |
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| 135 |
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| 136 | ; ***** TIMER_COUNTER_0 **************
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| 137 | ; TIMSK - Timer/Counter Interrupt Mask Register
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| 138 | .equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
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| 139 |
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| 140 | ; TIFR - Timer/Counter Interrupt Flag register
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| 141 | .equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
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| 142 |
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| 143 | ; TCCR0 - Timer/Counter0 Control Register
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| 144 | .equ CS00 = 0 ; Clock Select0 bit 0
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| 145 | .equ CS01 = 1 ; Clock Select0 bit 1
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| 146 | .equ CS02 = 2 ; Clock Select0 bit 2
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| 147 |
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| 148 | ; TCNT0 - Timer Counter 0
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| 149 | .equ TCNT00 = 0 ; Timer Counter 0 bit 0
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| 150 | .equ TCNT01 = 1 ; Timer Counter 0 bit 1
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| 151 | .equ TCNT02 = 2 ; Timer Counter 0 bit 2
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| 152 | .equ TCNT03 = 3 ; Timer Counter 0 bit 3
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| 153 | .equ TCNT04 = 4 ; Timer Counter 0 bit 4
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| 154 | .equ TCNT05 = 5 ; Timer Counter 0 bit 5
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| 155 | .equ TCNT06 = 6 ; Timer Counter 0 bit 6
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| 156 | .equ TCNT07 = 7 ; Timer Counter 0 bit 7
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| 157 |
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| 158 |
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| 159 | ; ***** TIMER_COUNTER_1 **************
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| 160 | ; TIMSK - Timer/Counter Interrupt Mask Register
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| 161 | .equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
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| 162 | .equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
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| 163 | .equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
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| 164 |
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| 165 | ; TIFR - Timer/Counter Interrupt Flag register
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| 166 | .equ ICF1 = 3 ; Input Capture Flag 1
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| 167 | .equ OCF1A = 6 ; Output Compare Flag 1A
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| 168 | .equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
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| 169 |
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| 170 | ; TCCR1A - Timer/Counter1 Control Register A
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| 171 | .equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
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| 172 | .equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
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| 173 | .equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
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| 174 | .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
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| 175 |
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| 176 | ; TCCR1B - Timer/Counter1 Control Register B
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| 177 | .equ CS10 = 0 ; Clock Select bit 0
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| 178 | .equ CS11 = 1 ; Clock Select 1 bit 1
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| 179 | .equ CS12 = 2 ; Clock Select1 bit 2
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| 180 | .equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
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| 181 | .equ ICES1 = 6 ; Input Capture 1 Edge Select
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| 182 | .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
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| 183 |
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| 184 |
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| 185 | ; ***** WATCHDOG *********************
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| 186 | ; WDTCR - Watchdog Timer Control Register
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| 187 | .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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| 188 | .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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| 189 | .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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| 190 | .equ WDE = 3 ; Watch Dog Enable
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| 191 | .equ WDTOE = 4 ; RW
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| 192 | .equ WDDE = WDTOE ; For compatibility
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| 193 |
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| 194 |
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| 195 | ; ***** EXTERNAL_INTERRUPT ***********
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| 196 | ; GIMSK - General Interrupt Mask Register
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| 197 | .equ INT0 = 6 ; External Interrupt Request 0 Enable
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| 198 | .equ INT1 = 7 ; External Interrupt Request 1 Enable
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| 199 |
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| 200 | ; GIFR - General Interrupt Flag register
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| 201 | .equ INTF0 = 6 ; External Interrupt Flag 0
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| 202 | .equ INTF1 = 7 ; External Interrupt Flag 1
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| 203 |
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| 204 |
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| 205 | ; ***** UART *************************
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| 206 | ; UDR - UART I/O Data Register
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| 207 | .equ UDR0 = 0 ; UART I/O Data Register bit 0
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| 208 | .equ UDR1 = 1 ; UART I/O Data Register bit 1
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| 209 | .equ UDR2 = 2 ; UART I/O Data Register bit 2
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| 210 | .equ UDR3 = 3 ; UART I/O Data Register bit 3
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| 211 | .equ UDR4 = 4 ; UART I/O Data Register bit 4
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| 212 | .equ UDR5 = 5 ; UART I/O Data Register bit 5
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| 213 | .equ UDR6 = 6 ; UART I/O Data Register bit 6
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| 214 | .equ UDR7 = 7 ; UART I/O Data Register bit 7
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| 215 |
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| 216 | ; USR - UART Status Register
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| 217 | .equ DOR = 3 ; Data overRun
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| 218 | .equ FE = 4 ; Framing Error
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| 219 | .equ UDRE = 5 ; UART Data Register Empty
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| 220 | .equ TXC = 6 ; UART Transmit Complete
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| 221 | .equ RXC = 7 ; UART Receive Complete
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| 222 |
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| 223 | ; UCR - UART Control Register
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| 224 | .equ TXB8 = 0 ; Transmit Data Bit 8
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| 225 | .equ RXB8 = 1 ; Receive Data Bit 8
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| 226 | .equ CHR9 = 2 ; 9-bit Characters
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| 227 | .equ TXEN = 3 ; Transmitter Enable
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| 228 | .equ RXEN = 4 ; Receiver Enable
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| 229 | .equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
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| 230 | .equ TXCIE = 6 ; TX Complete Interrupt Enable
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| 231 | .equ RXCIE = 7 ; RX Complete Interrupt Enable
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| 232 |
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| 233 | ; UBRR - UART BAUD Rate Register
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| 234 | .equ UBRR0 = 0 ; UART Baud Rate Register bit 0
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| 235 | .equ UBRR1 = 1 ; UART Baud Rate Register bit 1
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| 236 | .equ UBRR2 = 2 ; UART Baud Rate Register bit 2
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| 237 | .equ UBRR3 = 3 ; UART Baud Rate Register bit 3
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| 238 | .equ UBRR4 = 4 ; UART Baud Rate Register bit 4
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| 239 | .equ UBRR5 = 5 ; UART Baud Rate Register bit 5
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| 240 | .equ UBRR6 = 6 ; UART Baud Rate Register bit 6
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| 241 | .equ UBRR7 = 7 ; UART Baud Rate Register bit 7
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| 242 |
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| 243 |
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| 244 | ; ***** ANALOG_COMPARATOR ************
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| 245 | ; ACSR - Analog Comparator Control And Status Register
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| 246 | .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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| 247 | .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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| 248 | .equ ACIC = 2 ; Analog Comparator Input Capture Enable
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| 249 | .equ ACIE = 3 ; Analog Comparator Interrupt Enable
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| 250 | .equ ACI = 4 ; Analog Comparator Interrupt Flag
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| 251 | .equ ACO = 5 ; Analog Comparator Output
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| 252 | .equ ACD = 7 ; Analog Comparator Disable
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| 253 |
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| 254 |
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| 255 | ; ***** CPU **************************
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| 256 | ; SREG - Status Register
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| 257 | .equ SREG_C = 0 ; Carry Flag
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| 258 | .equ SREG_Z = 1 ; Zero Flag
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| 259 | .equ SREG_N = 2 ; Negative Flag
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| 260 | .equ SREG_V = 3 ; Two's Complement Overflow Flag
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| 261 | .equ SREG_S = 4 ; Sign Bit
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| 262 | .equ SREG_H = 5 ; Half Carry Flag
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| 263 | .equ SREG_T = 6 ; Bit Copy Storage
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| 264 | .equ SREG_I = 7 ; Global Interrupt Enable
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| 265 |
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| 266 | ; SPL - Stack Pointer Low
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| 267 | .equ SP0 = 0 ; Stack pointer bit 0
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| 268 | .equ SP1 = 1 ; Stack pointer bit 1
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| 269 | .equ SP2 = 2 ; Stack pointer bit 2
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| 270 | .equ SP3 = 3 ; Stack pointer bit 3
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| 271 | .equ SP4 = 4
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| 272 | .equ SP5 = 5 ; Stack pointer bit 5
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| 273 | .equ SP6 = 6 ; Stack pointer bit 6
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| 274 | .equ SP7 = 7 ; Stack pointer bit 7
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| 275 |
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| 276 | ; MCUCR - MCU Control Register
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| 277 | .equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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| 278 | .equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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| 279 | .equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
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| 280 | .equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
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| 281 | .equ SM = 4 ; Sleep Mode
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| 282 | .equ SE = 5 ; Sleep Enable
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| 283 |
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| 284 |
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| 285 | ; ***** PORTD ************************
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| 286 | ; PORTD - Data Register, Port D
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| 287 | .equ PORTD0 = 0 ;
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| 288 | .equ PD0 = 0 ; For compatibility
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| 289 | .equ PORTD1 = 1 ;
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| 290 | .equ PD1 = 1 ; For compatibility
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| 291 | .equ PORTD2 = 2 ;
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| 292 | .equ PD2 = 2 ; For compatibility
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| 293 | .equ PORTD3 = 3 ;
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| 294 | .equ PD3 = 3 ; For compatibility
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| 295 | .equ PORTD4 = 4 ;
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| 296 | .equ PD4 = 4 ; For compatibility
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| 297 | .equ PORTD5 = 5 ;
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| 298 | .equ PD5 = 5 ; For compatibility
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| 299 | .equ PORTD6 = 6 ;
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| 300 | .equ PD6 = 6 ; For compatibility
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| 301 |
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| 302 | ; DDRD
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| 303 | .equ DDD0 = 0 ;
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| 304 | .equ DDD1 = 1 ;
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| 305 | .equ DDD2 = 2 ;
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| 306 | .equ DDD3 = 3 ;
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| 307 | .equ DDD4 = 4 ;
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| 308 | .equ DDD5 = 5 ;
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| 309 | .equ DDD6 = 6 ;
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| 310 |
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| 311 | ; PIND - Input Pins, Port D
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| 312 | .equ PIND0 = 0 ;
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| 313 | .equ PIND1 = 1 ;
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| 314 | .equ PIND2 = 2 ;
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| 315 | .equ PIND3 = 3 ;
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| 316 | .equ PIND4 = 4 ;
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| 317 | .equ PIND5 = 5 ;
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| 318 | .equ PIND6 = 6 ;
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| 319 |
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| 320 |
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| 321 | ; ***** EEPROM ***********************
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| 322 | ; EEAR - EEPROM Read/Write Access
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| 323 | .equ EEARL = EEAR ; For compatibility
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| 324 | .equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
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| 325 | .equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
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| 326 | .equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
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| 327 | .equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
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| 328 | .equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
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| 329 | .equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
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| 330 | .equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
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| 331 |
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| 332 | ; EEDR - EEPROM Data Register
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| 333 | .equ EEDR0 = 0 ; EEPROM Data Register bit 0
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| 334 | .equ EEDR1 = 1 ; EEPROM Data Register bit 1
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| 335 | .equ EEDR2 = 2 ; EEPROM Data Register bit 2
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| 336 | .equ EEDR3 = 3 ; EEPROM Data Register bit 3
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| 337 | .equ EEDR4 = 4 ; EEPROM Data Register bit 4
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| 338 | .equ EEDR5 = 5 ; EEPROM Data Register bit 5
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| 339 | .equ EEDR6 = 6 ; EEPROM Data Register bit 6
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| 340 | .equ EEDR7 = 7 ; EEPROM Data Register bit 7
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| 341 |
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| 342 | ; EECR - EEPROM Control Register
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| 343 | .equ EERE = 0 ; EEPROM Read Enable
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| 344 | .equ EEWE = 1 ; EEPROM Write Enable
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| 345 | .equ EEMWE = 2 ; EEPROM Master Write Enable
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| 346 |
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| 347 |
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| 348 |
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| 349 | ; ***** LOCKSBITS ********************************************************
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| 350 | .equ LB1 = 0 ; Lockbit
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| 351 | .equ LB2 = 1 ; Lockbit
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| 352 |
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| 353 |
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| 354 | ; ***** FUSES ************************************************************
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| 355 | ; LOW fuse bits
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| 356 |
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| 357 |
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| 358 |
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| 359 | ; ***** CPU REGISTER DEFINITIONS *****************************************
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| 360 | .def XH = r27
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| 361 | .def XL = r26
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| 362 | .def YH = r29
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| 363 | .def YL = r28
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| 364 | .def ZH = r31
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| 365 | .def ZL = r30
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| 366 |
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| 367 |
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| 368 |
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| 369 | ; ***** DATA MEMORY DECLARATIONS *****************************************
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| 370 | .equ FLASHEND = 0x03ff ; Note: Word address
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| 371 | .equ IOEND = 0x003f
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| 372 | .equ SRAM_START = 0x0060
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| 373 | .equ SRAM_SIZE = 128
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| 374 | .equ RAMEND = 0x00df
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| 375 | .equ XRAMEND = 0x0000
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| 376 | .equ E2END = 0x007f
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| 377 | .equ EEPROMEND = 0x007f
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| 378 | .equ EEADRBITS = 7
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| 379 | #pragma AVRPART MEMORY PROG_FLASH 2048
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| 380 | #pragma AVRPART MEMORY EEPROM 128
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| 381 | #pragma AVRPART MEMORY INT_SRAM SIZE 128
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| 382 | #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
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| 383 |
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| 384 |
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| 385 |
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| 386 |
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| 387 |
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| 388 | ; ***** INTERRUPT VECTORS ************************************************
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| 389 | .equ INT0addr = 0x0001 ; External Interrupt Request 0
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| 390 | .equ INT1addr = 0x0002 ; External Interrupt Request 1
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| 391 | .equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
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| 392 | .equ OC1addr = 0x0004 ; Timer/Counter1 Compare Match
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| 393 | .equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
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| 394 | .equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
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| 395 | .equ URXCaddr = 0x0007 ; UART, Rx Complete
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| 396 | .equ UDREaddr = 0x0008 ; UART Data Register Empty
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| 397 | .equ UTXCaddr = 0x0009 ; UART, Tx Complete
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| 398 | .equ ACIaddr = 0x000a ; Analog Comparator
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| 399 |
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| 400 | .equ INT_VECTORS_SIZE = 11 ; size in words
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| 401 |
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| 402 | #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
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| 403 |
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| 404 | #endif /* _2313DEF_INC_ */
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| 405 |
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| 406 | ; ***** END OF FILE ******************************************************
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