Changeset 53d1ddc in avrstuff


Ignore:
Timestamp:
Oct 29, 2010, 6:24:23 PM (14 years ago)
Author:
Adrien Destugues <pulkomandy@…>
Branches:
main
Children:
741c0b9
Parents:
1dc9759
Message:

Now it is possible to assemble the code (with AVRA)

git-svn-id: svn://pulkomandy.tk/avrstuff@27 c6672c3c-f6b6-47f9-9001-1fd6b12fecbe

Location:
CPC stuff/cpc_serial_2313/code
Files:
1 added
1 edited

Legend:

Unmodified
Added
Removed
  • CPC stuff/cpc_serial_2313/code/main.asm

    r1dc9759 r53d1ddc  
    22; Copyright 2010, Adrien Destugues <pulkomandy@pulkomandy.ath.cx>
    33; Distributed under the terms of the MIT Licence
     4.INCLUDE "2313def.inc"
    45
    56; Firmware for µSerial expansion board
    67
     8.EQU ALL_OUT = 255
     9.EQU ALL_IN = 0
     10
     11.EQU DATADIR = DDRB
     12.EQU DATAOUT = PORTB
     13.EQU DATAIN = PINB
     14
     15.EQU CTRLIN = PIND
     16.EQU A0 = PIND4
     17
     18.EQU curregbak = SRAM_START
     19
     20.CSEG
    721; Vectors
    822; reset
     23        RJMP init
    924; int0
    1025        RJMP cpc_write
     
    2439
    2540; --- READ INTERRUPT ---
    26 cpc_read
     41cpc_read:
    2742; That means we only have 5 cycles left to output the value on the BUS!
    2843; We have no time to do anything, so we assume that X is already pointing at
     
    3853; We assume X (R26:R27) points to the current reg
    3954; So we can load it and react fast enough to the interrupt
    40         LDI R0,ALL_OUT ; 1 ; peut être économisé si on sacrifie un reg
     55        LDI R16,ALL_OUT ; 1 ; peut être économisé si on sacrifie un reg
    4156        OUT DATADIR,R0 ; 1
    42         LD R27,(X)                      ; 2 cycles ; peut être économisé si un reg. contient
     57        LD R27,X                        ; 2 cycles ; peut être économisé si un reg. contient
    4358                                                                        ; déjà la valeur à envoyer
    4459                                                                        ; (mais qui l'update ?)
    45         OUT DATA, R27           ; 1 cycle
     60        OUT DATAOUT, R27                ; 1 cycle
    4661
    4762; Here data is sent, the CPC read operation is handled.
     
    5368
    5469; Restore R27
    55         LD R27,curregbak
    56         LD R27,(X)
     70        LDI R27,curregbak
     71        LD R27,X
    5772
    5873; release the bus
    59         LDI R0,ALL_IN
    60         OUT DATADIR, R0
     74        LDI R16,ALL_IN
     75        OUT DATADIR, R16
    6176
    6277; Restore R27 to selected reg. (we erased it to do the OUT)
    6378        RETI
    6479
     80
    6581; --- WRITE INTERRUPT ---
    66 cpc_write
     82cpc_write:
    6783; The timing is a bit less constraining here.
    6884        PUSH R0
    69         IN R0,DATA
     85        IN R0,DATAIN
    7086; we also need to know A0 state...
    71         SBIS CTRL,A0
     87        SBIS CTRLIN,A0
    7288                ; This was actually a reg select operation!
    7389                ; Jump to the proper code
     
    7995        RJMP intEnd
    8096
    81 regSel
    82         LD R27,curregbak
    83         ST (X),R0
     97regSel:
     98        LDI R27,curregbak
     99        ST X,R0
    84100        MOV R27,R0
    85101
     102intEnd:
    86103        POP R0
    87104        RETI
     
    92109; At a bare minimum :
    93110; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself
     111init:
     112        RJMP init
Note: See TracChangeset for help on using the changeset viewer.