Changeset 741c0b9 in avrstuff
- Timestamp:
- Oct 29, 2010, 7:04:18 PM (14 years ago)
- Branches:
- main
- Children:
- 7d5e268
- Parents:
- 53d1ddc
- File:
-
- 1 edited
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- Unmodified
- Added
- Removed
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CPC stuff/cpc_serial_2313/code/main.asm
r53d1ddc r741c0b9 17 17 18 18 .EQU curregbak = SRAM_START 19 20 ; REGISTERS ALLOCATION 21 ; R0 = 255 used in interrupt handler for fast switching of DATADIR 22 ; X (R27 & R26) used in interrupt for fast addressing of regs 19 23 20 24 .CSEG … … 53 57 ; We assume X (R26:R27) points to the current reg 54 58 ; So we can load it and react fast enough to the interrupt 55 LDI R16,ALL_OUT ; 1 ; peut être économisé si on sacrifie un reg 56 OUT DATADIR,R0 ; 1 59 OUT DATADIR,R16 ; 1 57 60 LD R27,X ; 2 cycles ; peut être économisé si un reg. contient 58 61 ; déjà la valeur à envoyer 59 62 ; (mais qui l'update ?) 60 OUT DATAOUT, R27 63 OUT DATAOUT, R27 ; 1 cycle 61 64 62 65 ; Here data is sent, the CPC read operation is handled. … … 68 71 69 72 ; Restore R27 70 LDI R27,curregbak 71 LD R27,X 73 LDS R27,curregbak 72 74 73 75 ; release the bus 74 76 LDI R16,ALL_IN 75 77 OUT DATADIR, R16 78 LDI R16,ALL_OUT 76 79 77 80 ; Restore R27 to selected reg. (we erased it to do the OUT) … … 82 85 cpc_write: 83 86 ; The timing is a bit less constraining here. 84 PUSH R0 85 IN R0,DATAIN 87 PUSH R0 ; 2 cycles 88 IN R0,DATAIN ; 1 86 89 ; we also need to know A0 state... 87 SBIS CTRLIN,A0 90 SBIS CTRLIN,A0 ; 1 88 91 ; This was actually a reg select operation! 89 92 ; Jump to the proper code … … 96 99 97 100 regSel: 98 LDI R27,curregbak 99 ST X,R0 101 STS curregbak,R0 100 102 MOV R27,R0 101 103 … … 110 112 ; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself 111 113 init: 112 RJMP init 114 ; setup ctrl port : RW and A0 as inputs, INT as output 115 ; led on (will be turned off by software at init) 116 ; init serial port speed and io 117 ; check for bootloader jumper and jump to bootload code if needed 118 119 SEI 120 mainloop: 121 ; maybe we will have to handle a buffer for the serial port 122 ; and 'fake' registers in SRAM 123 124 SLEEP 125 RJMP mainloop
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