Changeset 741c0b9 in avrstuff


Ignore:
Timestamp:
Oct 29, 2010, 7:04:18 PM (14 years ago)
Author:
Adrien Destugues <pulkomandy@…>
Branches:
main
Children:
7d5e268
Parents:
53d1ddc
Message:

Some optimizations to get faster interrupts
Some comments in main to tell what it should be doing

git-svn-id: svn://pulkomandy.tk/avrstuff@28 c6672c3c-f6b6-47f9-9001-1fd6b12fecbe

File:
1 edited

Legend:

Unmodified
Added
Removed
  • CPC stuff/cpc_serial_2313/code/main.asm

    r53d1ddc r741c0b9  
    1717
    1818.EQU curregbak = SRAM_START
     19
     20; REGISTERS ALLOCATION
     21; R0 = 255 used in interrupt handler for fast switching of DATADIR
     22; X (R27 & R26) used in interrupt for fast addressing of regs
    1923
    2024.CSEG
     
    5357; We assume X (R26:R27) points to the current reg
    5458; So we can load it and react fast enough to the interrupt
    55         LDI R16,ALL_OUT ; 1 ; peut être économisé si on sacrifie un reg
    56         OUT DATADIR,R0 ; 1
     59        OUT DATADIR,R16         ; 1
    5760        LD R27,X                        ; 2 cycles ; peut être économisé si un reg. contient
    5861                                                                        ; déjà la valeur à envoyer
    5962                                                                        ; (mais qui l'update ?)
    60         OUT DATAOUT, R27                ; 1 cycle
     63        OUT DATAOUT, R27        ; 1 cycle
    6164
    6265; Here data is sent, the CPC read operation is handled.
     
    6871
    6972; Restore R27
    70         LDI R27,curregbak
    71         LD R27,X
     73        LDS R27,curregbak
    7274
    7375; release the bus
    7476        LDI R16,ALL_IN
    7577        OUT DATADIR, R16
     78        LDI R16,ALL_OUT
    7679
    7780; Restore R27 to selected reg. (we erased it to do the OUT)
     
    8285cpc_write:
    8386; The timing is a bit less constraining here.
    84         PUSH R0
    85         IN R0,DATAIN
     87        PUSH R0                                         ; 2 cycles
     88        IN R0,DATAIN                            ; 1
    8689; we also need to know A0 state...
    87         SBIS CTRLIN,A0
     90        SBIS CTRLIN,A0                          ; 1
    8891                ; This was actually a reg select operation!
    8992                ; Jump to the proper code
     
    9699
    97100regSel:
    98         LDI R27,curregbak
    99         ST X,R0
     101        STS curregbak,R0
    100102        MOV R27,R0
    101103
     
    110112; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself
    111113init:
    112         RJMP init
     114        ; setup ctrl port : RW and A0 as inputs, INT as output
     115        ; led on (will be turned off by software at init)
     116        ; init serial port speed and io
     117        ; check for bootloader jumper and jump to bootload code if needed
     118
     119        SEI
     120mainloop:
     121        ; maybe we will have to handle a buffer for the serial port
     122        ; and 'fake' registers in SRAM
     123
     124        SLEEP
     125        RJMP mainloop
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