1 | ; ---------------------------------------------------------------
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2 | ; Copyright 2010, Adrien Destugues <pulkomandy@pulkomandy.ath.cx>
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3 | ; Distributed under the terms of the MIT Licence
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4 | .INCLUDE "2313def.inc"
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5 |
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6 | ; Firmware for µSerial expansion board
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7 |
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8 | .EQU ALL_OUT = 255
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9 | .EQU ALL_IN = 0
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10 |
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11 | .EQU DATADIR = DDRB
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12 | .EQU DATAOUT = PORTB
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13 | .EQU DATAIN = PINB
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14 |
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15 | .EQU CTRLIN = PIND
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16 | .EQU A0 = PIND4
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17 |
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18 | .EQU curregbak = SRAM_START
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19 |
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20 | ; REGISTERS ALLOCATION
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21 | ; R0 = 255 used in interrupt handler for fast switching of DATADIR
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22 | ; X (R27 & R26) used in interrupt for fast addressing of regs
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23 |
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24 | .CSEG
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25 | ; Vectors
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26 | ; reset
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27 | RJMP init
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28 | ; int0
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29 | RJMP cpc_write
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30 | ; int1
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31 | RJMP cpc_read
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32 | ; ...
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33 |
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34 | ; Interrupt vectors for external INT pins (read and write).
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35 | ; we have to react very quick.
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36 | ; A read operation for the CPC lasts 3 clock cycles at 4MHz, that's 15
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37 | ; AVR cycles. But the interrupt latency is as follow :
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38 | ; Lowlevel detection ; 2 cycles
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39 | ; End of running instruction ; up to 2 cycles
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40 | ; Save PC ; 4 cycles
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41 | ;Vector RJMP ; 2 cycles
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42 | ; TOTAL => 10 cycles
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43 |
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44 | ; --- READ INTERRUPT ---
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45 | cpc_read:
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46 | ; That means we only have 5 cycles left to output the value on the BUS!
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47 | ; We have no time to do anything, so we assume that X is already pointing at
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48 | ; the right place and we just OUT it to the data port. We have no time for
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49 | ; PUSHing and loading it, anyway.
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50 |
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51 | ; Note you can read from either port and get the same result. Two reasons to
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52 | ; that : you can already access all the registers and part of the SRAM,
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53 | ; and there's no time to do something more clever.
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54 |
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55 | ; There is no time to push/pop regs, so we just use X as is. R27 is part of X.
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56 |
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57 | ; We assume X (R26:R27) points to the current reg
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58 | ; So we can load it and react fast enough to the interrupt
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59 | OUT DATADIR,R16 ; 1
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60 | LD R27,X ; 2 cycles ; peut être économisé si un reg. contient
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61 | ; déjà la valeur à envoyer
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62 | ; (mais qui l'update ?)
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63 | OUT DATAOUT, R27 ; 1 cycle
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64 |
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65 | ; Here data is sent, the CPC read operation is handled.
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66 | ; We now wait for the end of the read cycle.
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67 | ; This is not the end of the time-constrained nightmare, however :
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68 | ; In the worst case, the CPC can do another OUT or IN right after,
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69 | ; so we don't have an infinite number of cycles to handle the interrupt.
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70 | ; it is much more relaxed, as we have 12 CPC cycles = 60 AVR cycles free.
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71 |
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72 | ; Restore R27
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73 | LDS R27,curregbak
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74 |
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75 | ; release the bus
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76 | LDI R16,ALL_IN
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77 | OUT DATADIR, R16
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78 | LDI R16,ALL_OUT
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79 |
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80 | ; Restore R27 to selected reg. (we erased it to do the OUT)
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81 | RETI
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82 |
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83 |
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84 | ; --- WRITE INTERRUPT ---
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85 | cpc_write:
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86 | ; The timing is a bit less constraining here.
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87 | PUSH R0 ; 2 cycles
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88 | IN R0,DATAIN ; 1
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89 | ; we also need to know A0 state...
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90 | SBIS CTRLIN,A0 ; 1
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91 | ; This was actually a reg select operation!
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92 | ; Jump to the proper code
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93 | RJMP regSel
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94 | ; We have read the CPC data. End of the heavy-constraint area
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95 |
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96 | ; Register write
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97 | ST X,R0 ; Normal register write
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98 | RJMP intEnd
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99 |
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100 | regSel:
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101 | STS curregbak,R0
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102 | MOV R27,R0
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103 |
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104 | intEnd:
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105 | POP R0
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106 | RETI
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107 |
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108 |
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109 | ; --- RESET VECTOR ---
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110 | ; Here we perform the hardware initialization.
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111 | ; At a bare minimum :
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112 | ; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself
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113 | init:
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114 | ; setup ctrl port : RW and A0 as inputs, INT as output
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115 | ; led on (will be turned off by software at init)
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116 | ; init serial port speed and io
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117 | ; check for bootloader jumper and jump to bootload code if needed
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118 |
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119 | SEI
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120 | mainloop:
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121 | ; maybe we will have to handle a buffer for the serial port
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122 | ; and 'fake' registers in SRAM
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123 |
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124 | SLEEP
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125 | RJMP mainloop
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