[1dc9759] | 1 | ; ---------------------------------------------------------------
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| 2 | ; Copyright 2010, Adrien Destugues <pulkomandy@pulkomandy.ath.cx>
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| 3 | ; Distributed under the terms of the MIT Licence
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[53d1ddc] | 4 | .INCLUDE "2313def.inc"
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[1dc9759] | 5 |
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| 6 | ; Firmware for µSerial expansion board
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| 7 |
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[53d1ddc] | 8 | .EQU ALL_OUT = 255
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| 9 | .EQU ALL_IN = 0
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| 10 |
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| 11 | .EQU DATADIR = DDRB
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| 12 | .EQU DATAOUT = PORTB
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| 13 | .EQU DATAIN = PINB
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| 14 |
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| 15 | .EQU CTRLIN = PIND
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[7d5e268] | 16 | .EQU CTRLOUT = PORTD
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| 17 | .EQU CTRLDIR = DDRD
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| 18 |
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| 19 | .EQU A0 = PIND5
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| 20 | .EQU _READ = PIND3
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| 21 | .EQU _WRITE = PIND2
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| 22 | .EQU DEL = PIND6
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| 23 | .EQU INT = PIND4
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[53d1ddc] | 24 |
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| 25 | .EQU curregbak = SRAM_START
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| 26 |
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[741c0b9] | 27 | ; REGISTERS ALLOCATION
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| 28 | ; R0 = 255 used in interrupt handler for fast switching of DATADIR
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| 29 | ; X (R27 & R26) used in interrupt for fast addressing of regs
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| 30 |
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[53d1ddc] | 31 | .CSEG
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[1dc9759] | 32 | ; Vectors
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| 33 | ; reset
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[53d1ddc] | 34 | RJMP init
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[1dc9759] | 35 | ; int0
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| 36 | RJMP cpc_write
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| 37 | ; int1
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| 38 | RJMP cpc_read
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| 39 | ; ...
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| 40 |
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| 41 | ; Interrupt vectors for external INT pins (read and write).
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| 42 | ; we have to react very quick.
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| 43 | ; A read operation for the CPC lasts 3 clock cycles at 4MHz, that's 15
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| 44 | ; AVR cycles. But the interrupt latency is as follow :
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| 45 | ; Lowlevel detection ; 2 cycles
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| 46 | ; End of running instruction ; up to 2 cycles
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| 47 | ; Save PC ; 4 cycles
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| 48 | ;Vector RJMP ; 2 cycles
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| 49 | ; TOTAL => 10 cycles
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| 50 |
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| 51 | ; --- READ INTERRUPT ---
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[53d1ddc] | 52 | cpc_read:
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[1dc9759] | 53 | ; That means we only have 5 cycles left to output the value on the BUS!
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| 54 | ; We have no time to do anything, so we assume that X is already pointing at
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| 55 | ; the right place and we just OUT it to the data port. We have no time for
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| 56 | ; PUSHing and loading it, anyway.
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| 57 |
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| 58 | ; Note you can read from either port and get the same result. Two reasons to
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| 59 | ; that : you can already access all the registers and part of the SRAM,
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| 60 | ; and there's no time to do something more clever.
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| 61 |
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| 62 | ; There is no time to push/pop regs, so we just use X as is. R27 is part of X.
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| 63 |
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| 64 | ; We assume X (R26:R27) points to the current reg
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| 65 | ; So we can load it and react fast enough to the interrupt
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[741c0b9] | 66 | OUT DATADIR,R16 ; 1
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[53d1ddc] | 67 | LD R27,X ; 2 cycles ; peut être économisé si un reg. contient
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[1dc9759] | 68 | ; déjà la valeur à envoyer
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| 69 | ; (mais qui l'update ?)
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[741c0b9] | 70 | OUT DATAOUT, R27 ; 1 cycle
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[1dc9759] | 71 |
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| 72 | ; Here data is sent, the CPC read operation is handled.
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| 73 | ; We now wait for the end of the read cycle.
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| 74 | ; This is not the end of the time-constrained nightmare, however :
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| 75 | ; In the worst case, the CPC can do another OUT or IN right after,
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| 76 | ; so we don't have an infinite number of cycles to handle the interrupt.
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| 77 | ; it is much more relaxed, as we have 12 CPC cycles = 60 AVR cycles free.
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| 78 |
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| 79 | ; Restore R27
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[741c0b9] | 80 | LDS R27,curregbak
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[1dc9759] | 81 |
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| 82 | ; release the bus
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[7d5e268] | 83 | SER R16
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[53d1ddc] | 84 | OUT DATADIR, R16
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[7d5e268] | 85 | CLR R16
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[1dc9759] | 86 |
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| 87 | ; Restore R27 to selected reg. (we erased it to do the OUT)
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| 88 | RETI
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| 89 |
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[53d1ddc] | 90 |
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[1dc9759] | 91 | ; --- WRITE INTERRUPT ---
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[53d1ddc] | 92 | cpc_write:
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[1dc9759] | 93 | ; The timing is a bit less constraining here.
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[741c0b9] | 94 | PUSH R0 ; 2 cycles
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| 95 | IN R0,DATAIN ; 1
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[1dc9759] | 96 | ; we also need to know A0 state...
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[741c0b9] | 97 | SBIS CTRLIN,A0 ; 1
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[1dc9759] | 98 | ; This was actually a reg select operation!
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| 99 | ; Jump to the proper code
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| 100 | RJMP regSel
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| 101 | ; We have read the CPC data. End of the heavy-constraint area
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| 102 |
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| 103 | ; Register write
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| 104 | ST X,R0 ; Normal register write
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| 105 | RJMP intEnd
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| 106 |
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[53d1ddc] | 107 | regSel:
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[741c0b9] | 108 | STS curregbak,R0
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[1dc9759] | 109 | MOV R27,R0
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| 110 |
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[53d1ddc] | 111 | intEnd:
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[1dc9759] | 112 | POP R0
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| 113 | RETI
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| 114 |
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| 115 |
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| 116 | ; --- RESET VECTOR ---
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| 117 | ; Here we perform the hardware initialization.
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| 118 | ; At a bare minimum :
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| 119 | ; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself
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[53d1ddc] | 120 | init:
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[7d5e268] | 121 | CLI
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| 122 | ; setup ctrl port : RW and A0 as inputs, INT and DEL as output
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| 123 | LDI R16,0x28
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| 124 | OUT CTRLDIR,R16
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| 125 |
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| 126 | ; setup dataport as input
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| 127 | CLR R0
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| 128 | OUT DATADIR,R0
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| 129 |
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[741c0b9] | 130 | ; led on (will be turned off by software at init)
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[7d5e268] | 131 | SBI CTRLOUT,DEL
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| 132 |
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[741c0b9] | 133 | ; init serial port speed and io
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[7d5e268] | 134 | LDI R16,10
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| 135 | OUT UBRR,R16
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| 136 |
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[741c0b9] | 137 | ; check for bootloader jumper and jump to bootload code if needed
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[7d5e268] | 138 | ; TODO
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| 139 |
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| 140 | ; setup interrupts (enable INT0 and INT1 on falling edge)
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| 141 | LDI R16,0x0A
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| 142 | OUT MCUCR,R16
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[741c0b9] | 143 |
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[7d5e268] | 144 | LDI R16,0xC0
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| 145 | OUT GIMSK,R16
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| 146 |
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| 147 | ; we can now enable interrupts
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[741c0b9] | 148 | SEI
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[7d5e268] | 149 |
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[741c0b9] | 150 | mainloop:
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| 151 | ; maybe we will have to handle a buffer for the serial port
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| 152 | ; and 'fake' registers in SRAM
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| 153 |
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| 154 | SLEEP
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| 155 | RJMP mainloop
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