Changeset ea32107 in avrstuff for kbd/xtk/code/main.c
- Timestamp:
- Jul 31, 2014, 10:13:43 PM (10 years ago)
- Branches:
- main
- Children:
- 87ab18e
- Parents:
- c7cc629
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kbd/xtk/code/main.c
rc7cc629 rea32107 1 #define F_CPU 16000000UL2 3 1 #include <avr/io.h> 4 2 #include <avr/pgmspace.h> … … 39 37 init_keyboard(); // PS/2 KBD handler 40 38 41 // PCW init - configure pins directions42 PORTB = 0;43 DDRB = 0; // PB2 and PB1 as inputs (floating)44 39 45 //debug LED - output 46 DDRD |= (1<<PD6); 47 40 #ifdef __AVR_ATtiny2313__ 41 #define PORTXT PORTD 42 #define DDRXT DDRD 43 #define PINXT PIND 44 static const int PCLK = (1<<PD0); 45 static const int PDAT = (1<<PD1); 46 #else 47 #define PORTXT PORTB 48 #define DDRXT DDRB 49 #define PINXT PINB 48 50 static const int PCLK = (1<<PB1); 49 51 static const int PDAT = (1<<PB2); 52 #endif 53 54 static const int delay = 25; 55 56 // XT init - configure pins directions 57 PORTXT &= ~(PCLK | PDAT); 58 DDRXT &= ~(PCLK | PDAT); // both pins as inputs (floating) 59 60 DDRB |= (1<<PB2); // LED 50 61 51 62 uint8_t k; 52 63 while(1) { 53 while ((PINB & (PDAT|PCLK)) != (PDAT|PCLK)) 64 PORTB ^= (1<<PB2); // LED 65 66 while ((PINXT & (PDAT|PCLK)) != (PDAT|PCLK)) 54 67 ; // Wait for PC to be ready to receive data 55 68 56 69 while(key == 0xFF) 57 70 ; // Wait for data to send 58 59 PORTD ^= (1<<PD6);60 71 61 72 k = key; // local copy so we can receive another code from PS/2 … … 64 75 65 76 // SEND START BIT 66 DDR B&= ~PDAT; // DAT HI67 _delay_us( 50);68 DDR B|= PCLK; // CLK LOW69 _delay_us( 50);70 DDR B&= ~PCLK; // CLK HI77 DDRXT &= ~PDAT; // DAT HI 78 _delay_us(delay); 79 DDRXT |= PCLK; // CLK LOW 80 _delay_us(delay); 81 DDRXT &= ~PCLK; // CLK HI 71 82 72 83 for(int i = 0; i < 8; i++) 73 84 { 74 85 if (k & 1) 75 DDR B&= ~PDAT;86 DDRXT &= ~PDAT; 76 87 else 77 DDR B|= PDAT;88 DDRXT |= PDAT; 78 89 79 _delay_us( 50);80 DDR B|= PCLK; // CLK LOW81 _delay_us( 50);82 DDR B&= ~PCLK; // CLK HI90 _delay_us(delay); 91 DDRXT |= PCLK; // CLK LOW 92 _delay_us(delay); 93 DDRXT &= ~PCLK; // CLK HI 83 94 84 95 k >>= 1; 85 96 } 86 97 87 DDR B&= ~PDAT; // DAT HI98 DDRXT &= ~PDAT; // DAT HI 88 99 89 _delay_us( 100);100 _delay_us(delay * 2); 90 101 } 91 102
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