General information

The TO7 was built using only standard 74LSxx series logic chips. This led to a densely populated motherboard, costly machine, and complicated manufacturing. In order to save costs, all following machines will use one or several “gate array” chips, merging most of the logic into a single chip.

Lightpen management

On TO machines, E7E4 is writable. Writing bit 0 to 1 requests an update of the lightpen latched values. This makes the registers update only once, so the CPU can then safely process the latched data. The monitor ROM code does at least 2 scans, and up to 8, to filter the lightpen position and give a reliable result.

E7E4-5 / A7E4-5: SCRCLK

This register is latched when the lightpen detects the electron beam. It holds a copy of the screen generation clock at that time. This is then read by the FIRQ handler to compute the lightpen position.

E7E6 / A7E6: Line counter

  • bit 7: LT3
  • bit 6: INILN - “Inhibition Line”.

Bit 6 is 0 when the video generator is generating the vertical borders, on the right and left of the screen.

When the lightpen is not pointing to the pixel area of the screen, bit 7 allows to know if it points at the left or right border.

E7E7 / A7E7: INITN

  • bit 7: INITN
  • bit 6: Lightpen latched INITN

bit 7 is 0 when the video generator is generating horizontal borders, on the top and bottom of the screen. When both INITN and INILN are set to 1, the video generator is drawing pixels. This is one way to synchronize your code with the screen refresh.

Bit 6 is set to the value of INITN at the last lightpen detection. This allows to detect if the lightpen was out of the vertical pixel area.

On the page mode gate array, more information is available:

  • bit 5: INILN (0 when the electron beam is drawing left and right borders)
  • bit 1: FIRQ request state
  • bit 0: status of the gate array registers. When this bit is 0, the new system registers (see below) are mapped. When it is 1, the lightpen registers are mapped.

MO5

Video generation

The gate array reads 2 bytes at a time from the video memory, which is 2 banks of 8 8Ki*1bit chips. The address of the bytes to read is generated from several counters. Memory access is linear, starting at address 0.

For each block of 8 pixels, the bytes from the two pages are used as follows:

  • Page 0 is the “pixel” memory. Each pixel is represented by 1 bit, and is either set (foreground) or clear (background)
  • Page 1 is the “color” or “attribute” memory. It is split in 2 groups of 4 bits, defining the background and foreground colors.

The pixels for page 0 are stored in a shift register. One at a time, they are shifted and used as the input to a multiplexer, which allows either the foreground or background attributes to pass through. When the video generator is not generating pixels, all this logic is unused, and the color to display is set from the system PIA “border” bits.

In all cases, the 4 selected attribute bits are fed to a palette ROM. The colors are fixed to the following palette:

ValueName RGBPreview ValueName RGBPreview
0000Black 000@#000: 1000Gray AAA@#AAA:
0001Red F55@#F55: 1001Pink FAA@#FAA:
0010Green 0F0@#0F0: 1010Light Green AFA@#AFA:
0011Yellow FF0@#FF0: 1011Chicken YellowFFA@#FFA:
0100Blue 55F@#55F: 1100Light Blue 5AF@#5AF:
0101Magenta F0F@#F0F: 1101Parma Pink FAF@#FAF:
0110Cyan 5FF@#5FF: 1110Light Cyan AFF@#AFF:
0111White FFF@#FFF: 1111Orange FA5@#FA5:

This is the palette as specified in the “Manuel Technique du MO5”. It seems reasonably accurate but it seems there were changes to the blue (could be 00F), and possibly also the cyan and light blue. This should be checked against the real hardware. Moreover, this palette is not Gamma-corrected, and the previews may not be accurate because of this. The actual color shown depends on the monitor used, and results are different on an LCD monitor, a cathodic tube TV, and the original CRT monitor sold by Thomson.

Also note that the MO6 gets this wrong! The MO6 will default to a palette identical to the TO8 one. That other palette is more systematic and predictible, but some of the pure colors are not detected as well by the lightpen sensor. The MO6 can be configured to be closer to the MO5 using the palette instruction in BASIC, or by poking appropriate values to the palette IC.

Gate array versions

There are two different versions of the MO5 Gate Array, used in the first and second generation of machines.

TO9 gate arrays

Video generation

Register map

All registers are write only.

AddressNameDescription
E7DCLGAMOD Video mode
E7DDLGTOU Border color

E7DC: Video mode configuration

Bits Description
XT1T0φ1φ0CBATranscoding
0 0 Legacy mode
0 1 Direct mode
1 0 Special mode (TO8 and later)
1 1 Transposed mode
XT1T0φ1φ0CBADot clock
0 0 8MHz (40 columns)
0 1 16MHz (80 columns)
1 0 8MHz (40 columns) - unofficial (tested on MO6)
1 1 4MHz (20 columns)
XT1T0φ1φ0CBALayout
000TO7/70
001Bitmap 4
01080 columns
011Bitmap 16
100Page 1
101Page 2
110Overprint
111Triple overprint

At each cycle of the 1MHz CPU clock, two bytes are fetched from memory, one from each of the 8KB video pages. This register defines how they are combined to generate pixels on screen.

For legacy reasons, the high-order bit of colors is always flipped. This means 16-color modes use colors 8-15,0-7, in that order. 4 colors modes use colors 8-11, and 2 color modes use colors 8 and 12.

40 columns mode

This is the default video mode, and compatible with the earlier machines (TO7, TO7/70 and MO5). It is designed for use with an 8MHz dot clock.

The legacy transcoding is used to match the TO7 video memory structure, and transforms attribute RAM this way:

RAM content>Transcoded Data
AEFGHBCD>ABCDEFGH

It is often easier to disable this by using the direct transcoding instead.

In this mode, the first page is used as “pixel” RAM, and the second page is used as “attribute” RAM. The attributes define a foreground and a background color. The bits from the pixel RAM determines, for each pixel, which of these two colors is used.

RAM A RAM B Result on screen
00101001 A1A2A3A4B1B2B3B4 BBABABBA

If you set the transcoder to transposed mode, attributes and pixels are mixed in strange ways:

RAM A RAM B Result on screen
01A1B100A2B2 10A3B301A4B4 BBABABBA

I'm not sure this is useful. Prove me wrong!

And for reference, in special mode:

RAM A RAM B Result on screen
0A10A21A30A4 1B10B20B31B4 BBABABBA

Bitmap 4 mode

In this mode (transcoding in direct mode, 8MHz dot clock), the screen is 320×200 pixels, 4 colors, without constraints.

TranscodingRAM A RAM B Result on screen
Direct A1B1C1D1E1F1G1H1 A2B2C2D2E2F2G2H2 ABCDEFGH
Transposed A1E1A2E2B1F1B2F2 C1G1C2G2D1H1D2G2 ABCDEFGH
Special A1A2B1B2C1C2D1D2 E1E2F1F2G1G2H1H2 ABCDEFGH
  • In direct mode, each pixel uses one bit from each page
  • In tranposed mode, the two bits from each pixel are in the same page, but they are a bit out of order.
  • In special mode, everything is as expected. But this won't work on the TO9, only the TO8/9+/8D. Using this mode with a dot clock of 4MHz makes a 160×200, 4 color mode, using only one 8KB RAM page.

Bitmap 16 mode

In this mode (transcoding in bitmap 16 mode, 4MHz dot clock), the resolution is only 160×200 pixels, the 16 colors can be used and there are no constraints.

When setting the transcoder to bitmap 16 mode, the first RAM page defines colors for the first two pixels, and the second RAM page defines the colors for the two others.

Transcoding RAM A RAM B Result on screen
Direct A1A2A3A4B1B2B3B4 C1C2C3C4D1D2D3D4 ABCD
Transposed A1B1C1D1A2B2C2D2 A3B3C3D3A4B4C4D4 ABCD
Special A1C1A2C2A3C3A4C4 B1D1B2D2B3D3B4D4 ABCD
  • In direct mode, RAM A defines the first two pixels, and RAM B defines the next two.
  • In tranposed mode, this works as a partial bitplane mode, where each pixel gets one bit from each 4-bit nibble.
  • In special mode, RAM A define the even pixels, RAM B defines the odd ones. This can be useful as a 16-color 80×200 mode (with one page forced to black)

80 columns mode

In this mode (transcoding in direct mode, 16MHz dot clock), the resolution is 640×200 pixels, but only 2 colors are available.

RAM A defines the even pixels, and RAM B defines the odd ones:

TranscodingRAM A RAM B Result on screen
Direct ACEGIKMO BDFHJLNP ABCDEFGHIJKLMNOP
Transposed AIBJCKDL EMFNGOHP ABCDEFGHIJKLMNOP
Special ABCDEFGH IJKLMNOP ABCDEFGHIJKLMNOP
  • In direct mode, RAM A defines the even pixels, RAM B defines the odd ones.
  • In transposed mode, the organization doesn't make much sense.
  • In special mode, pixels are stored linearly. Easy.

Page 1 and Page 2 modes

These two modes allow working with one page at a time only. They have a resolution of 320×200 pixels, and only 2 colors. The pixels are defined in-order by one of the two pages.

  • When using page A, the colors used are number 8 and 9.
  • When using page B, the colors used are number 8 and 10.

This is designed for use with the direct transcoding. The transposed transcoding would split out the useful bits around in the two pages, defeating the purpose of these modes.

Overprint mode

This is a combination of the two “single page” modes.

  • If page A sets a 1 for the pixel, it uses color 9
  • Else, if page B sets a 1 for the pixel, it uses color 10
  • Else, it uses color 8.

Note that this is the same as the bitmap 4 mode with colors 10 and 11 set to the same value. Again, transposed transcoding may be used for more fun. See the bitmap4 tables.

Triple overprint mode

This is the most complex mode, and also probably the less useful one! It uses a 160×200 resolution, but allows only 5 colors: 0, 8, 9, 10, and 12.

The transcoder may be used in transcoded or direct mode, with the same effect as in bitmap16. This mode has the following color mappings:

  • Colors 0-7 all become color 0
  • Colors 12-15 all become color 12
  • Color 11 becomes color 10.

E7DD: Border color

4-bit value used as the palette index for the border color.

CF74021 "Page Mode" gate array

This is the final generation of gate array. Introduced in 1986, it can be configured in TO and MO modes, and is the chip used to build the MO6, MO5NR, TO8, TO9+, and TO8D, in various configurations.

The CF74021 retains compatibility with the previous features (video modes and light pen), and makes the registers writable to allow system control.

Register map

These register share addresses with the previous gate array registers. Where the old gate array was read-only, new functionality is introduced on writing.

Writing the A7E4/E7E4 register bit 0 allows to also enable reading some of these registers (not always at the same address where they are written…). This can be used to switch between these new functions and the legacy ones (lightpen management) for reading.

A7E7/E7E7: System register 1

This register is write only.

  • D7: Set this bit to disable the internal floppy controller, and allow use of an external one (TO only - the MO6 has no internal controller).
  • D6: Set this to enable the new RAM bank system for cartridge space using register A7E6/E7E6. If this bit is clear, the RAM works like the MO5 64K expansion.
  • D5: Display configuration. When this bit is set, the display generates 525 lines per frame (60Hz mode). When it is clear, there are 625 lines (50Hz mode, the default on French machines).
  • D4: Set this to enable the new RAM bank system for “data” space using register A7E5/E7E5. If this bit is clear, the braindead system using the two PIAs is used.
  • D3, D2: computer type.
    • 00 on MO6
    • 01 on TO9+
    • 11 on TO8
  • D1, D0: RAM type
    • 00 for 256Kx1 or 256Kx4 chips (TO8, TO9+)
    • 10 for 128Kx1 chips (MO6?)
    • 11 for 64Kx4 chips (?)

A7DD/E7DD (write) / A7E4/E7E4 (read): System register 2

These have new uses and can be read at A7E4/E7E4:

  • D7, D6: Select RAM page to use for display
    • Default is page 0
    • This doesn't affect the mapping for the CPU at address 0000 (MO) or 4000 (TO). If you want to write to the page, you must map it to the CPU.
  • D5: cartridge disable (MO only)
  • D4: BASIC ROM switch (MO only) - Setting to 0 selects legacy BASIC 1.0, setting to 1 selects BASIC 128.

These bits keep the old functions and are write only:

  • D3,D2,D1,D0 control the screen border color.

A7E5/E7E5: Data space RAM banking

This register is enabled by writing 1 to to A7E7/E7E7 bit 4. It replaces the previous RAM bank switching system, but also does a few other things.

These bits are write only:

  • D7: A7DC/E7DC write protect.
    • Setting this bit makes the gate array ignore all writes to A7DC/E7DC
    • This is useful because the QDD expansion also maps a register at the same address.
    • The QDD expansion must be mapped out (A7E7/E7E7 bit 7) when using the gate array, and the gate array must be write locked when using the QDD.
  • D6, D5: must be zero.

These are read/write:

  • D4-D0: RAM bank number (0 to 31) to map to data space (A000-DFFF on TO, 6000-9FFF on MO?)

Beware: the mapping in this bank flips the first and last 8K. Mapping the same page to different places, you'll get this:

Cartridge spaceData spaceScreen
0000-1FFF C000-DFFF RAM A (pixels)
2000-3FFF A000-BFFF RAM B (attributes)

A7E6/E7E6: Cartridge space RAM mapping

This register is write protected by A7E7/E7E7 bit 6 (write 1 there to enable writing here). It is read protected by A7E4/E7E4 bit 0 (write 1 there to enable reading here). All bits are read/write.

  • D7: must be zero
  • D6: write enable for the memory mapped in cartridge space
  • D5: enable RAM mapping for cartridge space (if 0, the ROM/cartridge is mapped instead)
  • D4-D0: RAM bank number (0 to 31) to map to cartridge space (0000-3FFF on TO, B000-EFFF on MO)

A7E4/E7E4: Read register switch

Only one writable bit here, bit 0. When set, reading from the Gate Array returns the usual light pen position values. When clear, the registers show extra information, partially replicating the write-only registers above with a different mapping.

documentations/devices/gate.arrays.txt · Last modified: 2015/02/28 18:08 (external edit)
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