| adamdunkels | 3023dee | 2003-07-04 10:54:51 +0000 | [diff] [blame] | 1 | #ifndef _DEV_RTLREGS_H_
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| 2 | #define _DEV_RTLREGS_H_
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| 3 |
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| 4 | /*
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| 5 | * Copyright (C) 2001-2002 by egnite Software GmbH. All rights reserved.
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| 6 | *
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| 7 | * Redistribution and use in source and binary forms, with or without
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| 8 | * modification, are permitted provided that the following conditions
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| 9 | * are met:
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| 10 | *
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| 11 | * 1. Redistributions of source code must retain the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer.
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| 13 | * 2. Redistributions in binary form must reproduce the above copyright
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| 14 | * notice, this list of conditions and the following disclaimer in the
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| 15 | * documentation and/or other materials provided with the distribution.
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| 16 | * 3. All advertising materials mentioning features or use of this
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| 17 | * software must display the following acknowledgement:
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| 18 | *
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| 19 | * This product includes software developed by egnite Software GmbH
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| 20 | * and its contributors.
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| 21 | *
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| 22 | * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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| 23 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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| 24 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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| 25 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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| 26 | * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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| 28 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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| 29 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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| 30 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 31 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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| 32 | * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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| 33 | * SUCH DAMAGE.
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| 34 | *
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| 35 | * For additional information see http://www.ethernut.de/
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| 36 | *
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| 37 | * -
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| 38 | * Portions Copyright (C) 2000 David J. Hudson <dave@humbug.demon.co.uk>
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| 39 | *
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| 40 | * This file is distributed in the hope that it will be useful, but WITHOUT
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| 41 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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| 42 | * FITNESS FOR A PARTICULAR PURPOSE.
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| 43 | *
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| 44 | * You can redistribute this file and/or modify it under the terms of the GNU
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| 45 | * General Public License (GPL) as published by the Free Software Foundation;
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| 46 | * either version 2 of the License, or (at your discretion) any later version.
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| 47 | * See the accompanying file "copying-gpl.txt" for more details.
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| 48 | *
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| 49 | * As a special exception to the GPL, permission is granted for additional
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| 50 | * uses of the text contained in this file. See the accompanying file
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| 51 | * "copying-liquorice.txt" for details.
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| 52 | * -
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| 53 | * Portions Copyright (c) 1983, 1993 by
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| 54 | * The Regents of the University of California. All rights reserved.
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| 55 | *
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| 56 | * Redistribution and use in source and binary forms, with or without
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| 57 | * modification, are permitted provided that the following conditions
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| 58 | * are met:
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| 59 | * 1. Redistributions of source code must retain the above copyright
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| 60 | * notice, this list of conditions and the following disclaimer.
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| 61 | * 2. Redistributions in binary form must reproduce the above copyright
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| 62 | * notice, this list of conditions and the following disclaimer in the
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| 63 | * documentation and/or other materials provided with the distribution.
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| 64 | * 3. All advertising materials mentioning features or use of this software
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| 65 | * must display the following acknowledgement:
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| 66 | * This product includes software developed by the University of
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| 67 | * California, Berkeley and its contributors.
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| 68 | * 4. Neither the name of the University nor the names of its contributors
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| 69 | * may be used to endorse or promote products derived from this software
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| 70 | * without specific prior written permission.
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| 71 | *
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| 72 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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| 73 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 74 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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| 75 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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| 76 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 77 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 78 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 79 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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| 80 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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| 81 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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| 82 | * SUCH DAMAGE.
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| 83 | */
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| 84 |
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| 85 | /*
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| 86 | * $Log: rtlregs.h,v $ |
| 87 | * Revision 1.1 2003/07/04 10:54:52 adamdunkels |
| 88 | * First version of the AVR port |
| 89 | * |
| 90 | * Revision 1.1 2003/02/05 20:49:07 adam |
| 91 | * *** empty log message *** |
| 92 | *
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| 93 | * Revision 1.6 2002/10/29 15:27:36 harald
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| 94 | * *** empty log message ***
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| 95 | *
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| 96 | * Revision 1.5 2002/06/26 17:29:08 harald
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| 97 | * First pre-release with 2.4 stack
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| 98 | *
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| 99 | */
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| 100 |
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| 101 | /*!
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| 102 | * \brief Realtek 8019AS register definitions.
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| 103 | */
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| 104 | /*@{*/
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| 105 |
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| 106 | /*
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| 107 | * Register offset applicable to all register pages.
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| 108 | */
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| 109 | #define NIC_CR 0x00 /*!< \brief Command register */
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| 110 | #define NIC_IOPORT 0x10 /*!< \brief I/O data port */
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| 111 | #define NIC_RESET 0x1f /*!< \brief Reset port */
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| 112 |
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| 113 | /*
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| 114 | * Page 0 register offsets.
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| 115 | */
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| 116 | #define NIC_PG0_CLDA0 0x01 /*!< \brief Current local DMA address 0 */
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| 117 | #define NIC_PG0_PSTART 0x01 /*!< \brief Page start register */
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| 118 | #define NIC_PG0_CLDA1 0x02 /*!< \brief Current local DMA address 1 */
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| 119 | #define NIC_PG0_PSTOP 0x02 /*!< \brief Page stop register */
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| 120 | #define NIC_PG0_BNRY 0x03 /*!< \brief Boundary pointer */
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| 121 | #define NIC_PG0_TSR 0x04 /*!< \brief Transmit status register */
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| 122 | #define NIC_PG0_TPSR 0x04 /*!< \brief Transmit page start address */
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| 123 | #define NIC_PG0_NCR 0x05 /*!< \brief Number of collisions register */
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| 124 | #define NIC_PG0_TBCR0 0x05 /*!< \brief Transmit byte count register 0 */
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| 125 | #define NIC_PG0_FIFO 0x06 /*!< \brief FIFO */
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| 126 | #define NIC_PG0_TBCR1 0x06 /*!< \brief Transmit byte count register 1 */
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| 127 | #define NIC_PG0_ISR 0x07 /*!< \brief Interrupt status register */
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| 128 | #define NIC_PG0_CRDA0 0x08 /*!< \brief Current remote DMA address 0 */
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| 129 | #define NIC_PG0_RSAR0 0x08 /*!< \brief Remote start address register 0
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| 130 | Low byte address to read from the buffer. */
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| 131 | #define NIC_PG0_CRDA1 0x09 /*!< \brief Current remote DMA address 1 */
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| 132 | #define NIC_PG0_RSAR1 0x09 /*!< \brief Remote start address register 1
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| 133 | High byte address to read from the buffer. */
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| 134 | #define NIC_PG0_RBCR0 0x0a /*!< \brief Remote byte count register 0
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| 135 | Low byte of the number of bytes to read
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| 136 | from the buffer. */
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| 137 | #define NIC_PG0_RBCR1 0x0b /*!< \brief Remote byte count register 1
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| 138 | High byte of the number of bytes to read
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| 139 | from the buffer. */
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| 140 | #define NIC_PG0_RSR 0x0c /*!< \brief Receive status register */
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| 141 | #define NIC_PG0_RCR 0x0c /*!< \brief Receive configuration register */
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| 142 | #define NIC_PG0_CNTR0 0x0d /*!< \brief Tally counter 0 (frame alignment errors) */
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| 143 | #define NIC_PG0_TCR 0x0d /*!< \brief Transmit configuration register */
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| 144 | #define NIC_PG0_CNTR1 0x0e /*!< \brief Tally counter 1 (CRC errors) */
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| 145 | #define NIC_PG0_DCR 0x0e /*!< \brief Data configuration register */
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| 146 | #define NIC_PG0_CNTR2 0x0f /*!< \brief Tally counter 2 (Missed packet errors) */
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| 147 | #define NIC_PG0_IMR 0x0f /*!< \brief Interrupt mask register */
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| 148 |
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| 149 | /*
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| 150 | * Page 1 register offsets.
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| 151 | */
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| 152 | #define NIC_PG1_PAR0 0x01 /*!< \brief Physical address register 0 */
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| 153 | #define NIC_PG1_PAR1 0x02 /*!< \brief Physical address register 1 */
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| 154 | #define NIC_PG1_PAR2 0x03 /*!< \brief Physical address register 2 */
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| 155 | #define NIC_PG1_PAR3 0x04 /*!< \brief Physical address register 3 */
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| 156 | #define NIC_PG1_PAR4 0x05 /*!< \brief Physical address register 4 */
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| 157 | #define NIC_PG1_PAR5 0x06 /*!< \brief Physical address register 5 */
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| 158 | #define NIC_PG1_CURR 0x07 /*!< \brief Current page register
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| 159 | The next incoming packet will be stored
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| 160 | at this page address. */
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| 161 | #define NIC_PG1_MAR0 0x08 /*!< \brief Multicast address register 0 */
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| 162 | #define NIC_PG1_MAR1 0x09 /*!< \brief Multicast address register 1 */
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| 163 | #define NIC_PG1_MAR2 0x0a /*!< \brief Multicast address register 2 */
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| 164 | #define NIC_PG1_MAR3 0x0b /*!< \brief Multicast address register 3 */
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| 165 | #define NIC_PG1_MAR4 0x0c /*!< \brief Multicast address register 4 */
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| 166 | #define NIC_PG1_MAR5 0x0d /*!< \brief Multicast address register 5 */
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| 167 | #define NIC_PG1_MAR6 0x0e /*!< \brief Multicast address register 6 */
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| 168 | #define NIC_PG1_MAR7 0x0f /*!< \brief Multicast address register 7 */
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| 169 |
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| 170 | /*
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| 171 | * Page 2 register offsets.
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| 172 | */
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| 173 | #define NIC_PG2_PSTART 0x01 /*!< \brief Page start register */
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| 174 | #define NIC_PG2_CLDA0 0x01 /*!< \brief Current local DMA address 0 */
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| 175 | #define NIC_PG2_PSTOP 0x02 /*!< \brief Page stop register */
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| 176 | #define NIC_PG2_CLDA1 0x02 /*!< \brief Current local DMA address 1 */
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| 177 | #define NIC_PG2_RNP 0x03 /*!< \brief Remote next packet pointer */
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| 178 | #define NIC_PG2_TSPR 0x04 /*!< \brief Transmit page start register */
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| 179 | #define NIC_PG2_LNP 0x05 /*!< \brief Local next packet pointer */
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| 180 | #define NIC_PG2_ACU 0x06 /*!< \brief Address counter (upper) */
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| 181 | #define NIC_PG2_ACL 0x07 /*!< \brief Address counter (lower) */
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| 182 | #define NIC_PG2_RCR 0x0c /*!< \brief Receive configuration register */
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| 183 | #define NIC_PG2_TCR 0x0d /*!< \brief Transmit configuration register */
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| 184 | #define NIC_PG2_DCR 0x0e /*!< \brief Data configuration register */
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| 185 | #define NIC_PG2_IMR 0x0f /*!< \brief Interrupt mask register */
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| 186 |
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| 187 | /*
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| 188 | * Page 3 register offsets.
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| 189 | */
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| 190 | #define NIC_PG3_EECR 0x01 /*!< \brief EEPROM command register */
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| 191 | #define NIC_PG3_BPAGE 0x02 /*!< \brief Boot-ROM page register */
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| 192 | #define NIC_PG3_CONFIG0 0x03 /*!< \brief Configuration register 0 (r/o) */
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| 193 | #define NIC_PG3_CONFIG1 0x04 /*!< \brief Configuration register 1 */
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| 194 | #define NIC_PG3_CONFIG2 0x05 /*!< \brief Configuration register 2 */
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| 195 | #define NIC_PG3_CONFIG3 0x06 /*!< \brief Configuration register 3 */
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| 196 | #define NIC_PG3_CSNSAV 0x08 /*!< \brief CSN save register (r/o) */
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| 197 | #define NIC_PG3_HLTCLK 0x09 /*!< \brief Halt clock */
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| 198 | #define NIC_PG3_INTR 0x0b /*!< \brief Interrupt pins (r/o) */
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| 199 |
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| 200 | /*
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| 201 | * Command register bits.
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| 202 | */
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| 203 | #define NIC_CR_STP 0x01 /*!< \brief Stop */
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| 204 | #define NIC_CR_STA 0x02 /*!< \brief Start */
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| 205 | #define NIC_CR_TXP 0x04 /*!< \brief Transmit packet */
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| 206 | #define NIC_CR_RD0 0x08 /*!< \brief Remote DMA command bit 0 */
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| 207 | #define NIC_CR_RD1 0x10 /*!< \brief Remote DMA command bit 1 */
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| 208 | #define NIC_CR_RD2 0x20 /*!< \brief Remote DMA command bit 2 */
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| 209 | #define NIC_CR_PS0 0x40 /*!< \brief Page select bit 0 */
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| 210 | #define NIC_CR_PS1 0x80 /*!< \brief Page select bit 1 */
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| 211 |
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| 212 | /*
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| 213 | * Interrupt status register bits.
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| 214 | */
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| 215 | #define NIC_ISR_PRX 0x01 /*!< \brief Packet received */
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| 216 | #define NIC_ISR_PTX 0x02 /*!< \brief Packet transmitted */
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| 217 | #define NIC_ISR_RXE 0x04 /*!< \brief Receive error */
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| 218 | #define NIC_ISR_TXE 0x08 /*!< \brief Transmit error */
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| 219 | #define NIC_ISR_OVW 0x10 /*!< \brief Overwrite warning */
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| 220 | #define NIC_ISR_CNT 0x20 /*!< \brief Counter overflow */
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| 221 | #define NIC_ISR_RDC 0x40 /*!< \brief Remote DMA complete */
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| 222 | #define NIC_ISR_RST 0x80 /*!< \brief Reset status */
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| 223 |
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| 224 | /*
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| 225 | * Interrupt mask register bits.
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| 226 | */
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| 227 | #define NIC_IMR_PRXE 0x01 /*!< \brief Packet received interrupt enable */
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| 228 | #define NIC_IMR_PTXE 0x02 /*!< \brief Packet transmitted interrupt enable */
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| 229 | #define NIC_IMR_RXEE 0x04 /*!< \brief Receive error interrupt enable */
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| 230 | #define NIC_IMR_TXEE 0x08 /*!< \brief Transmit error interrupt enable */
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| 231 | #define NIC_IMR_OVWE 0x10 /*!< \brief Overwrite warning interrupt enable */
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| 232 | #define NIC_IMR_CNTE 0x20 /*!< \brief Counter overflow interrupt enable */
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| 233 | #define NIC_IMR_RCDE 0x40 /*!< \brief Remote DMA complete interrupt enable */
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| 234 |
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| 235 | /*
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| 236 | * Data configuration register bits.
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| 237 | */
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| 238 | #define NIC_DCR_WTS 0x01 /*!< \brief Word transfer select */
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| 239 | #define NIC_DCR_BOS 0x02 /*!< \brief Byte order select */
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| 240 | #define NIC_DCR_LAS 0x04 /*!< \brief Long address select */
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| 241 | #define NIC_DCR_LS 0x08 /*!< \brief Loopback select */
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| 242 | #define NIC_DCR_AR 0x10 /*!< \brief Auto-initialize remote */
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| 243 | #define NIC_DCR_FT0 0x20 /*!< \brief FIFO threshold select bit 0 */
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| 244 | #define NIC_DCR_FT1 0x40 /*!< \brief FIFO threshold select bit 1 */
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| 245 |
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| 246 | /*
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| 247 | * Transmit configuration register bits.
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| 248 | */
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| 249 | #define NIC_TCR_CRC 0x01 /*!< \brief Inhibit CRC */
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| 250 | #define NIC_TCR_LB0 0x02 /*!< \brief Encoded loopback control bit 0 */
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| 251 | #define NIC_TCR_LB1 0x04 /*!< \brief Encoded loopback control bit 1 */
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| 252 | #define NIC_TCR_ATD 0x08 /*!< \brief Auto transmit disable */
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| 253 | #define NIC_TCR_OFST 0x10 /*!< \brief Collision offset enable */
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| 254 |
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| 255 | /*
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| 256 | * Transmit status register bits.
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| 257 | */
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| 258 | #define NIC_TSR_PTX 0x01 /*!< \brief Packet transmitted */
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| 259 | #define NIC_TSR_COL 0x04 /*!< \brief Transmit collided */
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| 260 | #define NIC_TSR_ABT 0x08 /*!< \brief Transmit aborted */
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| 261 | #define NIC_TSR_CRS 0x10 /*!< \brief Carrier sense lost */
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| 262 | #define NIC_TSR_FU 0x20 /*!< \brief FIFO underrun */
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| 263 | #define NIC_TSR_CDH 0x40 /*!< \brief CD heartbeat */
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| 264 | #define NIC_TSR_OWC 0x80 /*!< \brief Out of window collision */
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| 265 |
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| 266 | /*
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| 267 | * Receive configuration register bits.
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| 268 | */
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| 269 | #define NIC_RCR_SEP 0x01 /*!< \brief Save errored packets */
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| 270 | #define NIC_RCR_AR 0x02 /*!< \brief Accept runt packets */
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| 271 | #define NIC_RCR_AB 0x04 /*!< \brief Accept broadcast */
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| 272 | #define NIC_RCR_AM 0x08 /*!< \brief Accept multicast */
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| 273 | #define NIC_RCR_PRO 0x10 /*!< \brief Promiscuous physical */
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| 274 | #define NIC_RCR_MON 0x20 /*!< \brief Monitor mode */
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| 275 |
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| 276 | /*
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| 277 | * Receive status register bits.
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| 278 | */
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| 279 | #define NIC_RSR_PRX 0x01 /*!< \brief Packet received intact */
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| 280 | #define NIC_RSR_CRC 0x02 /*!< \brief CRC error */
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| 281 | #define NIC_RSR_FAE 0x04 /*!< \brief Frame alignment error */
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| 282 | #define NIC_RSR_FO 0x08 /*!< \brief FIFO overrun */
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| 283 | #define NIC_RSR_MPA 0x10 /*!< \brief Missed packet */
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| 284 | #define NIC_RSR_PHY 0x20 /*!< \brief Physical/multicast address */
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| 285 | #define NIC_RSR_DIS 0x40 /*!< \brief Receiver disabled */
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| 286 | #define NIC_RSR_DFR 0x80 /*!< \brief Deferring */
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| 287 |
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| 288 | /*
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| 289 | * EEPROM command register bits.
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| 290 | */
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| 291 | #define NIC_EECR_EEM1 0x80 /*!< \brief EEPROM Operating Mode */
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| 292 | #define NIC_EECR_EEM0 0x40 /*!< \brief EEPROM Operating Mode
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| 293 | - 0 0 Normal operation
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| 294 | - 0 1 Auto-load
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| 295 | - 1 0 9346 programming
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| 296 | - 1 1 Config register write enab */
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| 297 | #define NIC_EECR_EECS 0x08 /*!< \brief EEPROM Chip Select */
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| 298 | #define NIC_EECR_EESK 0x04 /*!< \brief EEPROM Clock */
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| 299 | #define NIC_EECR_EEDI 0x02 /*!< \brief EEPROM Data In */
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| 300 | #define NIC_EECR_EEDO 0x01 /*!< \brief EEPROM Data Out */
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| 301 |
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| 302 | /*
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| 303 | * Configuration register 2 bits.
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| 304 | */
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| 305 | #define NIC_CONFIG2_PL1 0x80 /*!< \brief Network media type */
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| 306 | #define NIC_CONFIG2_PL0 0x40 /*!< \brief Network media type
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| 307 | - 0 0 TP/CX auto-detect
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| 308 | - 0 1 10baseT
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| 309 | - 1 0 10base5
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| 310 | - 1 1 10base2 */
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| 311 | #define NIC_CONFIG2_BSELB 0x20 /*!< \brief BROM disable */
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| 312 | #define NIC_CONFIG2_BS4 0x10 /*!< \brief BROM size/base */
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| 313 | #define NIC_CONFIG2_BS3 0x08
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| 314 | #define NIC_CONFIG2_BS2 0x04
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| 315 | #define NIC_CONFIG2_BS1 0x02
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| 316 | #define NIC_CONFIG2_BS0 0x01
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| 317 |
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| 318 | /*
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| 319 | * Configuration register 3 bits
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| 320 | */
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| 321 | #define NIC_CONFIG3_PNP 0x80 /*!< \brief PnP Mode */
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| 322 | #define NIC_CONFIG3_FUDUP 0x40 /*!< \brief Full duplex */
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| 323 | #define NIC_CONFIG3_LEDS1 0x20 /*!< \brief LED1/2 pin configuration
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| 324 | - 0 LED1 == LED_RX, LED2 == LED_TX
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| 325 | - 1 LED1 == LED_CRS, LED2 == MCSB */
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| 326 | #define NIC_CONFIG3_LEDS0 0x10 /*!< \brief LED0 pin configration
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| 327 | - 0 LED0 pin == LED_COL
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| 328 | - 1 LED0 pin == LED_LINK */
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| 329 | #define NIC_CONFIG3_SLEEP 0x04 /*!< \brief Sleep mode */
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| 330 | #define NIC_CONFIG3_PWRDN 0x02 /*!< \brief Power Down */
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| 331 | #define NIC_CONFIG3_ACTIVEB 0x01 /*!< \brief inverse of bit 0 in PnP Act Reg */
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| 332 |
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| 333 | /*@}*/
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| 334 |
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| 335 | /*!
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| 336 | * \brief Read byte from controller register.
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| 337 | */
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| 338 | #define nic_read(reg) *(base + (reg))
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| 339 |
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| 340 | /*!
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| 341 | * \brief Write byte to controller register.
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| 342 | */
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| 343 | #define nic_write(reg, data) *(base + (reg)) = data
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| 344 |
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| 345 | #endif
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