| PulkoMandy | 17fc759 | 2022-07-28 18:27:54 +0200 | [diff] [blame] | 1 | /* Example backend for vbcc, it models a generic 32bit RISC or CISC |
| 2 | CPU. |
| 3 | |
| 4 | Configurable at build-time are: |
| 5 | - number of (32bit) general-purpose-registers |
| 6 | - number of (64bit) floating-point-registers |
| 7 | - number of (8bit) condition-code-registers |
| 8 | - mechanism for stack-arguments (moving ot fixed sp) |
| 9 | |
| 10 | It allows to select as run-time-options: |
| 11 | - two- or three-address code |
| 12 | - memory operands or load-store-architecture |
| 13 | - number of register-arguments |
| 14 | - number of caller-save-registers |
| 15 | */ |
| 16 | |
| 17 | /* buil-time configurable options: */ |
| 18 | #define NUM_GPRS 8 |
| 19 | #define NUM_FPRS 0 |
| 20 | #define NUM_CCRS 1 |
| 21 | #define FIXED_SP 0 |
| 22 | |
| 23 | #include "dt.h" |
| 24 | |
| 25 | /* internally used by the backend */ |
| 26 | #define FIRST_GPR 1 |
| 27 | #define LAST_GPR (FIRST_GPR+NUM_GPRS-1) |
| 28 | #define FIRST_FPR (LAST_GPR+1) |
| 29 | #define LAST_FPR (FIRST_FPR+NUM_FPRS-1) |
| 30 | #define FIRST_CCR (LAST_FPR+1) |
| 31 | #define LAST_CCR (FIRST_CCR+NUM_CCRS-1) |
| 32 | |
| 33 | /* This struct can be used to implement machine-specific */ |
| 34 | /* addressing-modes. */ |
| 35 | /* Currently possible are (const,gpr) and (gpr,gpr) */ |
| 36 | struct AddressingMode{ |
| 37 | int flags; |
| 38 | int base; |
| 39 | long offset; |
| 40 | }; |
| 41 | |
| 42 | /* The number of registers of the target machine. */ |
| 43 | #define MAXR NUM_GPRS+NUM_FPRS+NUM_CCRS |
| 44 | |
| 45 | /* Number of commandline-options the code-generator accepts. */ |
| 46 | #define MAXGF 20 |
| 47 | |
| 48 | /* If this is set to zero vbcc will not generate ICs where the */ |
| 49 | /* target operand is the same as the 2nd source operand. */ |
| 50 | /* This can sometimes simplify the code-generator, but usually */ |
| 51 | /* the code is better if the code-generator allows it. */ |
| 52 | #define USEQ2ASZ 1 |
| 53 | |
| 54 | /* This specifies the smallest integer type that can be added to a */ |
| 55 | /* pointer. */ |
| 56 | #define MINADDI2P INT |
| 57 | |
| 58 | /* If the bytes of an integer are ordered most significant byte */ |
| 59 | /* byte first and then decreasing set BIGENDIAN to 1. */ |
| 60 | #define BIGENDIAN 0 |
| 61 | |
| 62 | /* If the bytes of an integer are ordered lest significant byte */ |
| 63 | /* byte first and then increasing set LITTLEENDIAN to 1. */ |
| 64 | #define LITTLEENDIAN 1 |
| 65 | |
| 66 | /* Note that BIGENDIAN and LITTLEENDIAN are mutually exclusive. */ |
| 67 | |
| 68 | /* If switch-statements should be generated as a sequence of */ |
| 69 | /* SUB,TST,BEQ ICs rather than COMPARE,BEQ ICs set this to 1. */ |
| 70 | /* This can yield better code on some machines. */ |
| 71 | #define SWITCHSUBS 0 |
| 72 | |
| 73 | /* In optimizing compilation certain library memcpy/strcpy-calls */ |
| 74 | /* with length known at compile-time will be inlined using an */ |
| 75 | /* ASSIGN-IC if the size is less or equal to INLINEMEMCPY. */ |
| 76 | /* The type used for the ASSIGN-IC will be UNSIGNED|CHAR. */ |
| 77 | #define INLINEMEMCPY 1024 |
| 78 | |
| 79 | /* Parameters are sometimes passed in registers without __reg. */ |
| 80 | #define HAVE_REGPARMS 1 |
| 81 | |
| 82 | /* Parameters on the stack should be pushed in order rather than */ |
| 83 | /* in reverse order. */ |
| 84 | #define ORDERED_PUSH FIXED_SP |
| 85 | |
| 86 | /* Structure for reg_parm(). */ |
| 87 | struct reg_handle{ |
| 88 | unsigned long gregs; |
| 89 | unsigned long fregs; |
| 90 | }; |
| 91 | |
| 92 | /* We have some target-specific variable attributes. */ |
| 93 | #define HAVE_TARGET_ATTRIBUTES |
| 94 | |
| 95 | /* We have target-specific pragmas */ |
| 96 | #define HAVE_TARGET_PRAGMAS |
| 97 | |
| 98 | /* We keep track of all registers modified by a function. */ |
| 99 | #define HAVE_REGS_MODIFIED 1 |
| 100 | |
| 101 | /* We have a implement our own cost-functions to adapt |
| 102 | register-allocation */ |
| 103 | #define HAVE_TARGET_RALLOC 1 |
| 104 | #define cost_move_reg(x,y) 1 |
| 105 | #define cost_load_reg(x,y) 2 |
| 106 | #define cost_save_reg(x,y) 2 |
| 107 | #define cost_pushpop_reg(x) 3 |
| 108 | |
| 109 | /* size of buffer for asm-output, this can be used to do |
| 110 | peephole-optimizations of the generated assembly-output */ |
| 111 | #define EMIT_BUF_LEN 1024 /* should be enough */ |
| 112 | /* number of asm-output lines buffered */ |
| 113 | #define EMIT_BUF_DEPTH 4 |
| 114 | |
| 115 | /* We have no asm_peephole to optimize assembly-output */ |
| 116 | #define HAVE_TARGET_PEEPHOLE 0 |
| 117 | |
| 118 | /* we do not have a mark_eff_ics function, this is used to prevent |
| 119 | optimizations on code which can already be implemented by efficient |
| 120 | assembly */ |
| 121 | #undef HAVE_TARGET_EFF_IC |
| 122 | |
| 123 | /* we only need the standard data types (no bit-types, different pointers |
| 124 | etc.) */ |
| 125 | #undef HAVE_EXT_TYPES |
| 126 | #undef HAVE_TGT_PRINTVAL |
| 127 | |
| 128 | /* we do not need extra elements in the IC */ |
| 129 | #undef HAVE_EXT_IC |
| 130 | |
| 131 | /* we do not use unsigned int as size_t (but unsigned long, the default) */ |
| 132 | #undef HAVE_INT_SIZET |
| 133 | |
| 134 | /* we do not need register-pairs */ |
| 135 | #undef HAVE_REGPAIRS |
| 136 | |
| 137 | |
| 138 | /* do not create CONVERT ICs from integers smaller than int to floats */ |
| 139 | #define MIN_INT_TO_FLOAT_TYPE INT |
| 140 | |
| 141 | /* do not create CONVERT ICs from floats to ints smaller than int */ |
| 142 | #define MIN_FLOAT_TO_INT_TYPE INT |
| 143 | |
| 144 | /* do not create CONVERT_ICs from floats to unsigned integers */ |
| 145 | #define AVOID_FLOAT_TO_UNSIGNED 1 |
| 146 | |
| 147 | /* do not create CONVERT_ICs from unsigned integers to floats */ |
| 148 | #define AVOID_UNSIGNED_TO_FLOAT 1 |
| 149 | |
| 150 | /* convert multiplications/division by powers of two to shifts */ |
| 151 | #define HAVE_POF2OPT 1 |
| 152 | |
| 153 | #define HAVE_WANTBNE 1 |