PulkoMandy | 17fc759 | 2022-07-28 18:27:54 +0200 | [diff] [blame] | 1 | /* Example of a code-generator for a PowerPC */ |
| 2 | |
| 3 | #include "dt.h" |
| 4 | |
| 5 | /* This struct can be used to implement machine-specific */ |
| 6 | /* addressing-modes. */ |
| 7 | /* Not used in this code-generrator. */ |
| 8 | struct AddressingMode{ |
| 9 | int flags; |
| 10 | int base; |
| 11 | long offset; |
| 12 | }; |
| 13 | |
| 14 | /* The number of registers of the target machine. */ |
| 15 | #define MAXR 87 |
| 16 | |
| 17 | /* Number of commandline-options the code-generator accepts. */ |
| 18 | #define MAXGF 30 |
| 19 | |
| 20 | /* If this is set to zero vbcc will not generate ICs where the */ |
| 21 | /* target operand is the same as the 2nd source operand. */ |
| 22 | /* This can sometimes simplify the code-generator, but usually */ |
| 23 | /* the code is better if the code-generator allows it. */ |
| 24 | #define USEQ2ASZ 1 |
| 25 | |
| 26 | /* This specifies the smallest integer type that can be added to a */ |
| 27 | /* pointer. */ |
| 28 | #define MINADDI2P INT |
| 29 | |
| 30 | /* This specifies the largest integer type that can be added to a */ |
| 31 | /* pointer. */ |
| 32 | #define MAXADDI2P LONG |
| 33 | |
| 34 | #define HAVE_INT_SIZET 1 |
| 35 | |
| 36 | /* If the bytes of an integer are ordered most significant byte */ |
| 37 | /* byte first and then decreasing set BIGENDIAN to 1. */ |
| 38 | #define BIGENDIAN 1 |
| 39 | |
| 40 | /* If the bytes of an integer are ordered lest significant byte */ |
| 41 | /* byte first and then increasing set LITTLEENDIAN to 1. */ |
| 42 | #define LITTLEENDIAN 0 |
| 43 | |
| 44 | /* Note that BIGENDIAN and LITTLEENDIAN are mutually exclusive. */ |
| 45 | |
| 46 | /* If switch-statements should be generated as a sequence of */ |
| 47 | /* SUB,TST,BEQ ICs rather than COMPARE,BEQ ICs set this to 1. */ |
| 48 | /* This can yield better code on some machines. */ |
| 49 | #define SWITCHSUBS 0 |
| 50 | |
| 51 | /* In optimizing compilation certain library memcpy/strcpy-calls */ |
| 52 | /* with length known at compile-time will be inlined using an */ |
| 53 | /* ASSIGN-IC if the size is less or equal to INLINEMEMCPY. */ |
| 54 | /* The type used for the ASSIGN-IC will be UNSIGNED|CHAR. */ |
| 55 | #define INLINEMEMCPY 256 |
| 56 | |
| 57 | /* Parameters are sometimes passed in registers without __reg. */ |
| 58 | #define HAVE_REGPARMS 1 |
| 59 | |
| 60 | /* Parameters on the stack should be pushed in order rather than */ |
| 61 | /* in reverse order. */ |
| 62 | #define ORDERED_PUSH 1 |
| 63 | |
| 64 | /* Structure for reg_parm(). */ |
| 65 | struct reg_handle{ |
| 66 | unsigned long gregs; |
| 67 | unsigned long fregs; |
| 68 | }; |
| 69 | |
| 70 | /* We have some target-specific variable attributes. */ |
| 71 | #define HAVE_TARGET_ATTRIBUTES |
| 72 | |
| 73 | /* We have target-specific pragmas */ |
| 74 | #define HAVE_TARGET_PRAGMAS |
| 75 | |
| 76 | /* We keep track of all registers modified by a function. */ |
| 77 | #define HAVE_REGS_MODIFIED 1 |
| 78 | |
| 79 | #define HAVE_TARGET_RALLOC 1 |
| 80 | #define cost_move_reg(x,y) 1 |
| 81 | #define cost_load_reg(x,y) 2 |
| 82 | #define cost_save_reg(x,y) 2 |
| 83 | #define cost_pushpop_reg(x) 3 |
| 84 | |
| 85 | /* size of buffer for asm-output */ |
| 86 | #define EMIT_BUF_LEN 1024 /* should be enough */ |
| 87 | /* number of asm-output lines buffered */ |
| 88 | #define EMIT_BUF_DEPTH 4 |
| 89 | |
| 90 | /* We have no asm_peephole to optimize assembly-output */ |
| 91 | #define HAVE_TARGET_PEEPHOLE 0 |
| 92 | |
| 93 | /* we have a mark_eff_ics function */ |
| 94 | #define HAVE_TARGET_EFF_IC 1 |
| 95 | |
| 96 | /* we have register-pairs */ |
| 97 | #define HAVE_REGPAIRS 1 |
| 98 | |
| 99 | #define JUMP_TABLE_DENSITY 0.8 |
| 100 | #define JUMP_TABLE_LENGTH 12 |
| 101 | |
| 102 | /* This type will be added to every IC. Can be used by the cg. */ |
| 103 | #define HAVE_EXT_IC 1 |
| 104 | struct ext_ic { |
| 105 | int setcc; |
| 106 | }; |
| 107 | |
| 108 | /* OSEK support */ |
| 109 | #define HAVE_OSEK 1 |
| 110 | |
| 111 | /* We use builtin libcalls for some operations */ |
| 112 | #define HAVE_LIBCALLS 1 |
| 113 | |
| 114 | /* support for variable-length arrays */ |
| 115 | #define ALLOCVLA_REG 4 |
| 116 | #if 0 |
| 117 | #define ALLOCVLA_INLINEASM "\tlwz\t0,0(1)\n"\ |
| 118 | "\taddi\t3,3,7\n"\ |
| 119 | "\tsrwi\t3,3,3\n"\ |
| 120 | "\tslwi\t3,3,3\n"\ |
| 121 | "\tneg\t11,3\n"\ |
| 122 | "\tsub\t3,1,3\n"\ |
| 123 | "\tsubi\t11,11,8\n"\ |
| 124 | "\tstwux\t0,1,11" |
| 125 | #endif |
| 126 | #define ALLOCVLA_INLINEASM "\tlwz\t0,0(1)\n"\ |
| 127 | "\tneg\t3,3\n"\ |
| 128 | "\tsrwi\t3,3,3\n"\ |
| 129 | "\tslwi\t3,3,3\n"\ |
| 130 | "\tstwux\t0,1,3\n"\ |
| 131 | "\taddi\t3,1,____fo" |
| 132 | #define FREEVLA_REG 6 |
| 133 | #define FREEVLA_INLINEASM "\tlwz\t0,0(1)\n"\ |
| 134 | "\tmr\t1,5\n"\ |
| 135 | "\tstw\t0,0(1)" |
| 136 | #define OLDSPVLA_INLINEASM "\tmr\t3,1" |
| 137 | #define FPVLA_REG 32 |