source: avrstuff/CPC stuff/ramcard/ramcard.kicad_pro

main
Last change on this file was 029735c, checked in by PulkoMandy <pulkomandy@…>, 7 months ago

Update Ramcard schematics to Kicad 7 and fix an error on ROM enable

(files submitted by Zik, thanks!)

  • Property mode set to 100644
File size: 9.0 KB
Line 
1{
2 "board": {
3 "design_settings": {
4 "defaults": {
5 "board_outline_line_width": 0.381,
6 "copper_line_width": 0.381,
7 "copper_text_italic": false,
8 "copper_text_size_h": 1.524,
9 "copper_text_size_v": 2.032,
10 "copper_text_thickness": 0.30479999999999996,
11 "copper_text_upright": false,
12 "courtyard_line_width": 0.049999999999999996,
13 "dimension_precision": 4,
14 "dimension_units": 3,
15 "dimensions": {
16 "arrow_length": 1270000,
17 "extension_offset": 500000,
18 "keep_text_aligned": true,
19 "suppress_zeroes": false,
20 "text_position": 0,
21 "units_format": 1
22 },
23 "fab_line_width": 0.09999999999999999,
24 "fab_text_italic": false,
25 "fab_text_size_h": 1.0,
26 "fab_text_size_v": 1.0,
27 "fab_text_thickness": 0.15,
28 "fab_text_upright": false,
29 "other_line_width": 0.381,
30 "other_text_italic": false,
31 "other_text_size_h": 1.524,
32 "other_text_size_v": 1.524,
33 "other_text_thickness": 0.30479999999999996,
34 "other_text_upright": false,
35 "pads": {
36 "drill": 0.8128,
37 "height": 1.524,
38 "width": 1.524
39 },
40 "silk_line_width": 0.381,
41 "silk_text_italic": false,
42 "silk_text_size_h": 1.524,
43 "silk_text_size_v": 1.524,
44 "silk_text_thickness": 0.30479999999999996,
45 "silk_text_upright": false,
46 "zones": {
47 "45_degree_only": false,
48 "min_clearance": 0.508
49 }
50 },
51 "diff_pair_dimensions": [],
52 "drc_exclusions": [],
53 "meta": {
54 "filename": "board_design_settings.json",
55 "version": 2
56 },
57 "rule_severities": {
58 "annular_width": "error",
59 "clearance": "error",
60 "copper_edge_clearance": "error",
61 "courtyards_overlap": "error",
62 "diff_pair_gap_out_of_range": "error",
63 "diff_pair_uncoupled_length_too_long": "error",
64 "drill_out_of_range": "error",
65 "duplicate_footprints": "warning",
66 "extra_footprint": "warning",
67 "footprint_type_mismatch": "error",
68 "hole_clearance": "error",
69 "hole_near_hole": "error",
70 "invalid_outline": "error",
71 "item_on_disabled_layer": "error",
72 "items_not_allowed": "error",
73 "length_out_of_range": "error",
74 "malformed_courtyard": "error",
75 "microvia_drill_out_of_range": "error",
76 "missing_courtyard": "ignore",
77 "missing_footprint": "warning",
78 "net_conflict": "warning",
79 "npth_inside_courtyard": "ignore",
80 "padstack": "error",
81 "pth_inside_courtyard": "ignore",
82 "shorting_items": "error",
83 "silk_over_copper": "warning",
84 "silk_overlap": "warning",
85 "skew_out_of_range": "error",
86 "through_hole_pad_without_hole": "error",
87 "too_many_vias": "error",
88 "track_dangling": "warning",
89 "track_width": "error",
90 "tracks_crossing": "error",
91 "unconnected_items": "error",
92 "unresolved_variable": "error",
93 "via_dangling": "warning",
94 "zone_has_empty_net": "error",
95 "zones_intersect": "error"
96 },
97 "rules": {
98 "allow_blind_buried_vias": false,
99 "allow_microvias": false,
100 "max_error": 0.005,
101 "min_clearance": 0.0,
102 "min_copper_edge_clearance": 0.1905,
103 "min_hole_clearance": 0.25,
104 "min_hole_to_hole": 0.25,
105 "min_microvia_diameter": 0.508,
106 "min_microvia_drill": 0.127,
107 "min_silk_clearance": 0.0,
108 "min_through_hole_diameter": 0.508,
109 "min_track_width": 0.381,
110 "min_via_annular_width": 0.049999999999999996,
111 "min_via_diameter": 0.889,
112 "use_height_for_length_calcs": true
113 },
114 "track_widths": [
115 0.381
116 ],
117 "via_dimensions": [
118 {
119 "diameter": 1.50114,
120 "drill": 0.39878
121 }
122 ],
123 "zones_allow_external_fillets": false,
124 "zones_use_no_outline": true
125 },
126 "layer_presets": []
127 },
128 "boards": [],
129 "cvpcb": {
130 "equivalence_files": []
131 },
132 "erc": {
133 "erc_exclusions": [],
134 "meta": {
135 "version": 0
136 },
137 "pin_map": [
138 [
139 0,
140 0,
141 0,
142 0,
143 0,
144 0,
145 1,
146 0,
147 0,
148 0,
149 0,
150 2
151 ],
152 [
153 0,
154 2,
155 0,
156 1,
157 0,
158 0,
159 1,
160 0,
161 2,
162 2,
163 2,
164 2
165 ],
166 [
167 0,
168 0,
169 0,
170 0,
171 0,
172 0,
173 1,
174 0,
175 1,
176 0,
177 1,
178 2
179 ],
180 [
181 0,
182 1,
183 0,
184 0,
185 0,
186 0,
187 1,
188 1,
189 2,
190 1,
191 1,
192 2
193 ],
194 [
195 0,
196 0,
197 0,
198 0,
199 0,
200 0,
201 1,
202 0,
203 0,
204 0,
205 0,
206 2
207 ],
208 [
209 0,
210 0,
211 0,
212 0,
213 0,
214 0,
215 0,
216 0,
217 0,
218 0,
219 0,
220 2
221 ],
222 [
223 1,
224 1,
225 1,
226 1,
227 1,
228 0,
229 1,
230 1,
231 1,
232 1,
233 1,
234 2
235 ],
236 [
237 0,
238 0,
239 0,
240 1,
241 0,
242 0,
243 1,
244 0,
245 0,
246 0,
247 0,
248 2
249 ],
250 [
251 0,
252 2,
253 1,
254 2,
255 0,
256 0,
257 1,
258 0,
259 2,
260 2,
261 2,
262 2
263 ],
264 [
265 0,
266 2,
267 0,
268 1,
269 0,
270 0,
271 1,
272 0,
273 2,
274 0,
275 0,
276 2
277 ],
278 [
279 0,
280 2,
281 1,
282 1,
283 0,
284 0,
285 1,
286 0,
287 2,
288 0,
289 0,
290 2
291 ],
292 [
293 2,
294 2,
295 2,
296 2,
297 2,
298 2,
299 2,
300 2,
301 2,
302 2,
303 2,
304 2
305 ]
306 ],
307 "rule_severities": {
308 "bus_definition_conflict": "error",
309 "bus_entry_needed": "error",
310 "bus_label_syntax": "error",
311 "bus_to_bus_conflict": "error",
312 "bus_to_net_conflict": "error",
313 "different_unit_footprint": "error",
314 "different_unit_net": "error",
315 "duplicate_reference": "error",
316 "duplicate_sheet_names": "error",
317 "extra_units": "error",
318 "global_label_dangling": "warning",
319 "hier_label_mismatch": "error",
320 "label_dangling": "error",
321 "lib_symbol_issues": "warning",
322 "multiple_net_names": "warning",
323 "net_not_bus_member": "warning",
324 "no_connect_connected": "warning",
325 "no_connect_dangling": "warning",
326 "pin_not_connected": "error",
327 "pin_not_driven": "error",
328 "pin_to_pin": "warning",
329 "power_pin_not_driven": "error",
330 "similar_labels": "warning",
331 "unannotated": "error",
332 "unit_value_mismatch": "error",
333 "unresolved_variable": "error",
334 "wire_dangling": "error"
335 }
336 },
337 "libraries": {
338 "pinned_footprint_libs": [],
339 "pinned_symbol_libs": []
340 },
341 "meta": {
342 "filename": "ramcard.kicad_pro",
343 "version": 1
344 },
345 "net_settings": {
346 "classes": [
347 {
348 "bus_width": 12.0,
349 "clearance": 0.2,
350 "diff_pair_gap": 0.25,
351 "diff_pair_via_gap": 0.25,
352 "diff_pair_width": 0.2,
353 "line_style": 0,
354 "microvia_diameter": 0.3,
355 "microvia_drill": 0.1,
356 "name": "Default",
357 "pcb_color": "rgba(0, 0, 0, 0.000)",
358 "schematic_color": "rgba(0, 0, 0, 0.000)",
359 "track_width": 0.25,
360 "via_diameter": 0.8,
361 "via_drill": 0.4,
362 "wire_width": 6.0
363 }
364 ],
365 "meta": {
366 "version": 2
367 },
368 "net_colors": null
369 },
370 "pcbnew": {
371 "last_paths": {
372 "gencad": "",
373 "idf": "",
374 "netlist": "ramcard.net",
375 "specctra_dsn": "",
376 "step": "",
377 "vrml": ""
378 },
379 "page_layout_descr_file": ""
380 },
381 "schematic": {
382 "annotate_start_num": 0,
383 "drawing": {
384 "default_line_thickness": 6.0,
385 "default_text_size": 50.0,
386 "field_names": [],
387 "intersheets_ref_own_page": false,
388 "intersheets_ref_prefix": "",
389 "intersheets_ref_short": false,
390 "intersheets_ref_show": false,
391 "intersheets_ref_suffix": "",
392 "junction_size_choice": 3,
393 "label_size_ratio": 0.25,
394 "pin_symbol_size": 0.0,
395 "text_offset_ratio": 0.08
396 },
397 "legacy_lib_dir": "",
398 "legacy_lib_list": [],
399 "meta": {
400 "version": 1
401 },
402 "net_format_name": "",
403 "ngspice": {
404 "fix_include_paths": true,
405 "fix_passive_vals": false,
406 "meta": {
407 "version": 0
408 },
409 "model_mode": 0,
410 "workbook_filename": ""
411 },
412 "page_layout_descr_file": "",
413 "plot_directory": "",
414 "spice_adjust_passive_values": false,
415 "spice_external_command": "spice \"%I\"",
416 "subpart_first_id": 65,
417 "subpart_id_separator": 0
418 },
419 "sheets": [
420 [
421 "8ff9b81b-f39b-41e8-a2aa-c0403a3adebb",
422 ""
423 ]
424 ],
425 "text_variables": {}
426}
Note: See TracBrowser for help on using the repository browser.