1 | /* Name: usbdrvasm165.inc
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2 | * Project: AVR USB driver
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3 | * Author: Christian Starkjohann
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4 | * Creation Date: 2007-04-22
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5 | * Tabsize: 4
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6 | * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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7 | * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
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8 | * Revision: $Id: usbdrvasm165.inc 692 2008-11-07 15:07:40Z cs $
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9 | */
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10 |
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11 | /* Do not link this file! Link usbdrvasm.S instead, which includes the
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12 | * appropriate implementation!
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13 | */
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14 |
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15 | /*
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16 | General Description:
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17 | This file is the 16.5 MHz version of the USB driver. It is intended for the
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18 | ATTiny45 and similar controllers running on 16.5 MHz internal RC oscillator.
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19 | This version contains a phase locked loop in the receiver routine to cope with
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20 | slight clock rate deviations of up to +/- 1%.
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21 |
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22 | See usbdrv.h for a description of the entire driver.
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23 |
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24 | Since almost all of this code is timing critical, don't change unless you
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25 | really know what you are doing! Many parts require not only a maximum number
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26 | of CPU cycles, but even an exact number of cycles!
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27 | */
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28 |
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29 | ;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
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30 | ;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
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31 | ;max allowable interrupt latency: 59 cycles -> max 52 cycles interrupt disable
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32 | ;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes
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33 | ;nominal frequency: 16.5 MHz -> 11 cycles per bit
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34 | ; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%)
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35 | ; Numbers in brackets are clocks counted from center of last sync bit
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36 | ; when instruction starts
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37 |
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38 |
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39 | USB_INTR_VECTOR:
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40 | ;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt
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41 | push YL ;[-23] push only what is necessary to sync with edge ASAP
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42 | in YL, SREG ;[-21]
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43 | push YL ;[-20]
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44 | ;----------------------------------------------------------------------------
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45 | ; Synchronize with sync pattern:
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46 | ;----------------------------------------------------------------------------
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47 | ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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48 | ;sync up with J to K edge during sync pattern -- use fastest possible loops
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49 | ;The first part waits at most 1 bit long since we must be in sync pattern.
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50 | ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
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51 | ;waitForJ, ensure that this prerequisite is met.
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52 | waitForJ:
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53 | inc YL
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54 | sbis USBIN, USBMINUS
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55 | brne waitForJ ; just make sure we have ANY timeout
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56 | waitForK:
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57 | ;The following code results in a sampling window of < 1/4 bit which meets the spec.
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58 | sbis USBIN, USBMINUS ;[-15]
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59 | rjmp foundK ;[-14]
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60 | sbis USBIN, USBMINUS
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61 | rjmp foundK
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62 | sbis USBIN, USBMINUS
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63 | rjmp foundK
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64 | sbis USBIN, USBMINUS
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65 | rjmp foundK
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66 | sbis USBIN, USBMINUS
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67 | rjmp foundK
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68 | sbis USBIN, USBMINUS
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69 | rjmp foundK
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70 | #if USB_COUNT_SOF
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71 | lds YL, usbSofCount
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72 | inc YL
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73 | sts usbSofCount, YL
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74 | #endif /* USB_COUNT_SOF */
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75 | #ifdef USB_SOF_HOOK
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76 | USB_SOF_HOOK
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77 | #endif
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78 | rjmp sofError
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79 | foundK: ;[-12]
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80 | ;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
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81 | ;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
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82 | ;are cycles from center of first sync (double K) bit after the instruction
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83 | push r0 ;[-12]
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84 | ; [---] ;[-11]
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85 | push YH ;[-10]
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86 | ; [---] ;[-9]
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87 | lds YL, usbInputBufOffset;[-8]
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88 | ; [---] ;[-7]
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89 | clr YH ;[-6]
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90 | subi YL, lo8(-(usbRxBuf));[-5] [rx loop init]
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91 | sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init]
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92 | mov r0, x2 ;[-3] [rx loop init]
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93 | sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
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94 | rjmp haveTwoBitsK ;[-1]
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95 | pop YH ;[0] undo the pushes from before
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96 | pop r0 ;[2]
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97 | rjmp waitForK ;[4] this was not the end of sync, retry
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98 | ; The entire loop from waitForK until rjmp waitForK above must not exceed two
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99 | ; bit times (= 22 cycles).
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100 |
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101 | ;----------------------------------------------------------------------------
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102 | ; push more registers and initialize values while we sample the first bits:
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103 | ;----------------------------------------------------------------------------
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104 | haveTwoBitsK: ;[1]
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105 | push shift ;[1]
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106 | push x1 ;[3]
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107 | push x2 ;[5]
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108 | push x3 ;[7]
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109 | ldi shift, 0xff ;[9] [rx loop init]
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110 | ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag
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111 |
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112 | in x1, USBIN ;[11] <-- sample bit 0
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113 | bst x1, USBMINUS ;[12]
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114 | bld shift, 0 ;[13]
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115 | push x4 ;[14] == phase
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116 | ; [---] ;[15]
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117 | push cnt ;[16]
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118 | ; [---] ;[17]
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119 | ldi phase, 0 ;[18] [rx loop init]
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120 | ldi cnt, USB_BUFSIZE;[19] [rx loop init]
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121 | rjmp rxbit1 ;[20]
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122 | ; [---] ;[21]
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123 |
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124 | ;----------------------------------------------------------------------------
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125 | ; Receiver loop (numbers in brackets are cycles within byte after instr)
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126 | ;----------------------------------------------------------------------------
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127 | /*
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128 | byte oriented operations done during loop:
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129 | bit 0: store data
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130 | bit 1: SE0 check
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131 | bit 2: overflow check
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132 | bit 3: catch up
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133 | bit 4: rjmp to achieve conditional jump range
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134 | bit 5: PLL
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135 | bit 6: catch up
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136 | bit 7: jump, fixup bitstuff
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137 | ; 87 [+ 2] cycles
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138 | ------------------------------------------------------------------
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139 | */
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140 | continueWithBit5:
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141 | in x2, USBIN ;[055] <-- bit 5
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142 | eor r0, x2 ;[056]
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143 | or phase, r0 ;[057]
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144 | sbrc phase, USBMINUS ;[058]
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145 | lpm ;[059] optional nop3; modifies r0
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146 | in phase, USBIN ;[060] <-- phase
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147 | eor x1, x2 ;[061]
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148 | bst x1, USBMINUS ;[062]
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149 | bld shift, 5 ;[063]
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150 | andi shift, 0x3f ;[064]
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151 | in x1, USBIN ;[065] <-- bit 6
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152 | breq unstuff5 ;[066] *** unstuff escape
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153 | eor phase, x1 ;[067]
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154 | eor x2, x1 ;[068]
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155 | bst x2, USBMINUS ;[069]
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156 | bld shift, 6 ;[070]
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157 | didUnstuff6: ;[ ]
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158 | in r0, USBIN ;[071] <-- phase
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159 | cpi shift, 0x02 ;[072]
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160 | brlo unstuff6 ;[073] *** unstuff escape
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161 | didUnstuff5: ;[ ]
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162 | nop2 ;[074]
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163 | ; [---] ;[075]
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164 | in x2, USBIN ;[076] <-- bit 7
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165 | eor x1, x2 ;[077]
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166 | bst x1, USBMINUS ;[078]
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167 | bld shift, 7 ;[079]
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168 | didUnstuff7: ;[ ]
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169 | eor r0, x2 ;[080]
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170 | or phase, r0 ;[081]
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171 | in r0, USBIN ;[082] <-- phase
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172 | cpi shift, 0x04 ;[083]
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173 | brsh rxLoop ;[084]
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174 | ; [---] ;[085]
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175 | unstuff7: ;[ ]
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176 | andi x3, ~0x80 ;[085]
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177 | ori shift, 0x80 ;[086]
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178 | in x2, USBIN ;[087] <-- sample stuffed bit 7
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179 | nop ;[088]
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180 | rjmp didUnstuff7 ;[089]
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181 | ; [---] ;[090]
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182 | ;[080]
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183 |
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184 | unstuff5: ;[067]
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185 | eor phase, x1 ;[068]
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186 | andi x3, ~0x20 ;[069]
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187 | ori shift, 0x20 ;[070]
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188 | in r0, USBIN ;[071] <-- phase
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189 | mov x2, x1 ;[072]
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190 | nop ;[073]
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191 | nop2 ;[074]
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192 | ; [---] ;[075]
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193 | in x1, USBIN ;[076] <-- bit 6
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194 | eor r0, x1 ;[077]
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195 | or phase, r0 ;[078]
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196 | eor x2, x1 ;[079]
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197 | bst x2, USBMINUS ;[080]
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198 | bld shift, 6 ;[081] no need to check bitstuffing, we just had one
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199 | in r0, USBIN ;[082] <-- phase
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200 | rjmp didUnstuff5 ;[083]
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201 | ; [---] ;[084]
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202 | ;[074]
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203 |
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204 | unstuff6: ;[074]
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205 | andi x3, ~0x40 ;[075]
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206 | in x1, USBIN ;[076] <-- bit 6 again
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207 | ori shift, 0x40 ;[077]
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208 | nop2 ;[078]
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209 | ; [---] ;[079]
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210 | rjmp didUnstuff6 ;[080]
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211 | ; [---] ;[081]
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212 | ;[071]
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213 |
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214 | unstuff0: ;[013]
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215 | eor r0, x2 ;[014]
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216 | or phase, r0 ;[015]
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217 | andi x2, USBMASK ;[016] check for SE0
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218 | in r0, USBIN ;[017] <-- phase
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219 | breq didUnstuff0 ;[018] direct jump to se0 would be too long
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220 | andi x3, ~0x01 ;[019]
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221 | ori shift, 0x01 ;[020]
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222 | mov x1, x2 ;[021] mov existing sample
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223 | in x2, USBIN ;[022] <-- bit 1 again
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224 | rjmp didUnstuff0 ;[023]
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225 | ; [---] ;[024]
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226 | ;[014]
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227 |
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228 | unstuff1: ;[024]
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229 | eor r0, x1 ;[025]
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230 | or phase, r0 ;[026]
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231 | andi x3, ~0x02 ;[027]
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232 | in r0, USBIN ;[028] <-- phase
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233 | ori shift, 0x02 ;[029]
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234 | mov x2, x1 ;[030]
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235 | rjmp didUnstuff1 ;[031]
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236 | ; [---] ;[032]
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237 | ;[022]
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238 |
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239 | unstuff2: ;[035]
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240 | eor r0, x2 ;[036]
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241 | or phase, r0 ;[037]
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242 | andi x3, ~0x04 ;[038]
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243 | in r0, USBIN ;[039] <-- phase
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244 | ori shift, 0x04 ;[040]
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245 | mov x1, x2 ;[041]
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246 | rjmp didUnstuff2 ;[042]
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247 | ; [---] ;[043]
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248 | ;[033]
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249 |
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250 | unstuff3: ;[043]
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251 | in x2, USBIN ;[044] <-- bit 3 again
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252 | eor r0, x2 ;[045]
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253 | or phase, r0 ;[046]
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254 | andi x3, ~0x08 ;[047]
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255 | ori shift, 0x08 ;[048]
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256 | nop ;[049]
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257 | in r0, USBIN ;[050] <-- phase
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258 | rjmp didUnstuff3 ;[051]
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259 | ; [---] ;[052]
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260 | ;[042]
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261 |
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262 | unstuff4: ;[053]
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263 | andi x3, ~0x10 ;[054]
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264 | in x1, USBIN ;[055] <-- bit 4 again
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265 | ori shift, 0x10 ;[056]
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266 | rjmp didUnstuff4 ;[057]
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267 | ; [---] ;[058]
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268 | ;[048]
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269 |
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270 | rxLoop: ;[085]
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271 | eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others
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272 | in x1, USBIN ;[000] <-- bit 0
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273 | st y+, x3 ;[001]
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274 | ; [---] ;[002]
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275 | eor r0, x1 ;[003]
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276 | or phase, r0 ;[004]
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277 | eor x2, x1 ;[005]
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278 | in r0, USBIN ;[006] <-- phase
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279 | ser x3 ;[007]
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280 | bst x2, USBMINUS ;[008]
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281 | bld shift, 0 ;[009]
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282 | andi shift, 0xf9 ;[010]
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283 | rxbit1: ;[ ]
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284 | in x2, USBIN ;[011] <-- bit 1
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285 | breq unstuff0 ;[012] *** unstuff escape
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286 | andi x2, USBMASK ;[013] SE0 check for bit 1
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287 | didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff
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288 | breq se0 ;[014]
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289 | eor r0, x2 ;[015]
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290 | or phase, r0 ;[016]
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291 | in r0, USBIN ;[017] <-- phase
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292 | eor x1, x2 ;[018]
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293 | bst x1, USBMINUS ;[019]
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294 | bld shift, 1 ;[020]
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295 | andi shift, 0xf3 ;[021]
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296 | didUnstuff1: ;[ ]
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297 | in x1, USBIN ;[022] <-- bit 2
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298 | breq unstuff1 ;[023] *** unstuff escape
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299 | eor r0, x1 ;[024]
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300 | or phase, r0 ;[025]
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301 | subi cnt, 1 ;[026] overflow check
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302 | brcs overflow ;[027]
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303 | in r0, USBIN ;[028] <-- phase
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304 | eor x2, x1 ;[029]
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305 | bst x2, USBMINUS ;[030]
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306 | bld shift, 2 ;[031]
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307 | andi shift, 0xe7 ;[032]
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308 | didUnstuff2: ;[ ]
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309 | in x2, USBIN ;[033] <-- bit 3
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310 | breq unstuff2 ;[034] *** unstuff escape
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311 | eor r0, x2 ;[035]
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312 | or phase, r0 ;[036]
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313 | eor x1, x2 ;[037]
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314 | bst x1, USBMINUS ;[038]
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315 | in r0, USBIN ;[039] <-- phase
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316 | bld shift, 3 ;[040]
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317 | andi shift, 0xcf ;[041]
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318 | didUnstuff3: ;[ ]
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319 | breq unstuff3 ;[042] *** unstuff escape
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320 | nop ;[043]
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321 | in x1, USBIN ;[044] <-- bit 4
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322 | eor x2, x1 ;[045]
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323 | bst x2, USBMINUS ;[046]
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324 | bld shift, 4 ;[047]
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325 | didUnstuff4: ;[ ]
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326 | eor r0, x1 ;[048]
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327 | or phase, r0 ;[049]
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328 | in r0, USBIN ;[050] <-- phase
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329 | andi shift, 0x9f ;[051]
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330 | breq unstuff4 ;[052] *** unstuff escape
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331 | rjmp continueWithBit5;[053]
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332 | ; [---] ;[054]
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333 |
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334 | macro POP_STANDARD ; 16 cycles
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335 | pop cnt
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336 | pop x4
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337 | pop x3
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338 | pop x2
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339 | pop x1
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340 | pop shift
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341 | pop YH
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342 | pop r0
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343 | endm
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344 | macro POP_RETI ; 5 cycles
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345 | pop YL
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346 | out SREG, YL
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347 | pop YL
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348 | endm
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349 |
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350 | #include "asmcommon.inc"
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351 |
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352 |
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353 | ; USB spec says:
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354 | ; idle = J
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355 | ; J = (D+ = 0), (D- = 1)
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356 | ; K = (D+ = 1), (D- = 0)
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357 | ; Spec allows 7.5 bit times from EOP to SOP for replies
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358 |
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359 | bitstuff7:
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360 | eor x1, x4 ;[4]
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361 | ldi x2, 0 ;[5]
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362 | nop2 ;[6] C is zero (brcc)
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363 | rjmp didStuff7 ;[8]
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364 |
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365 | bitstuffN:
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366 | eor x1, x4 ;[5]
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367 | ldi x2, 0 ;[6]
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368 | lpm ;[7] 3 cycle NOP, modifies r0
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369 | out USBOUT, x1 ;[10] <-- out
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370 | rjmp didStuffN ;[0]
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371 |
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372 | #define bitStatus x3
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373 |
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374 | sendNakAndReti:
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375 | ldi cnt, USBPID_NAK ;[-19]
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376 | rjmp sendCntAndReti ;[-18]
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377 | sendAckAndReti:
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378 | ldi cnt, USBPID_ACK ;[-17]
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379 | sendCntAndReti:
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380 | mov r0, cnt ;[-16]
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381 | ldi YL, 0 ;[-15] R0 address is 0
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382 | ldi YH, 0 ;[-14]
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383 | ldi cnt, 2 ;[-13]
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384 | ; rjmp usbSendAndReti fallthrough
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385 |
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386 | ;usbSend:
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387 | ;pointer to data in 'Y'
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388 | ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
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389 | ;uses: x1...x4, shift, cnt, Y
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390 | ;Numbers in brackets are time since first bit of sync pattern is sent
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391 | usbSendAndReti: ; 12 cycles until SOP
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392 | in x2, USBDDR ;[-12]
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393 | ori x2, USBMASK ;[-11]
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394 | sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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395 | in x1, USBOUT ;[-8] port mirror for tx loop
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396 | out USBDDR, x2 ;[-7] <- acquire bus
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397 | ; need not init x2 (bitstuff history) because sync starts with 0
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398 | ldi x4, USBMASK ;[-6] exor mask
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399 | ldi shift, 0x80 ;[-5] sync byte is first byte sent
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400 | ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes
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401 | byteloop:
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402 | bitloop:
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403 | sbrs shift, 0 ;[8] [-3]
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404 | eor x1, x4 ;[9] [-2]
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405 | out USBOUT, x1 ;[10] [-1] <-- out
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406 | ror shift ;[0]
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407 | ror x2 ;[1]
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408 | didStuffN:
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409 | cpi x2, 0xfc ;[2]
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410 | brcc bitstuffN ;[3]
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411 | nop ;[4]
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412 | subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37
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413 | brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value
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---|
414 | sbrs shift, 0 ;[7]
|
---|
415 | eor x1, x4 ;[8]
|
---|
416 | ror shift ;[9]
|
---|
417 | didStuff7:
|
---|
418 | out USBOUT, x1 ;[10] <-- out
|
---|
419 | ror x2 ;[0]
|
---|
420 | cpi x2, 0xfc ;[1]
|
---|
421 | brcc bitstuff7 ;[2]
|
---|
422 | ld shift, y+ ;[3]
|
---|
423 | dec cnt ;[5]
|
---|
424 | brne byteloop ;[6]
|
---|
425 | ;make SE0:
|
---|
426 | cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
|
---|
427 | lds x2, usbNewDeviceAddr;[8]
|
---|
428 | lsl x2 ;[10] we compare with left shifted address
|
---|
429 | out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
|
---|
430 | ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
|
---|
431 | ;set address only after data packet was sent, not after handshake
|
---|
432 | subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0
|
---|
433 | sbci YH, 0 ;[1]
|
---|
434 | breq skipAddrAssign ;[2]
|
---|
435 | sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
|
---|
436 | skipAddrAssign:
|
---|
437 | ;end of usbDeviceAddress transfer
|
---|
438 | ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
|
---|
439 | USB_STORE_PENDING(x2) ;[5]
|
---|
440 | ori x1, USBIDLE ;[6]
|
---|
441 | in x2, USBDDR ;[7]
|
---|
442 | cbr x2, USBMASK ;[8] set both pins to input
|
---|
443 | mov x3, x1 ;[9]
|
---|
444 | cbr x3, USBMASK ;[10] configure no pullup on both pins
|
---|
445 | ldi x4, 4 ;[11]
|
---|
446 | se0Delay:
|
---|
447 | dec x4 ;[12] [15] [18] [21]
|
---|
448 | brne se0Delay ;[13] [16] [19] [22]
|
---|
449 | out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
|
---|
450 | out USBDDR, x2 ;[24] <-- release bus now
|
---|
451 | out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
|
---|
452 | rjmp doReturn
|
---|
453 |
|
---|