adamdunkels | 3023dee | 2003-07-04 10:54:51 +0000 | [diff] [blame] | 1 | #include "rtl8019.h" |
| 2 | #include "delay.h" |
| 3 | #include "debug.h" |
| 4 | #include "avr/pgmspace.h" |
| 5 | #include "rtlregs.h" |
| 6 | |
| 7 | |
| 8 | /***************************************************************************** |
| 9 | * Module Name: Realtek 8019AS Driver |
| 10 | * |
| 11 | * Created By: Louis Beaudoin (www.embedded-creations.com) |
| 12 | * |
| 13 | * Original Release: September 21, 2002 |
| 14 | * |
| 15 | * Module Description: |
| 16 | * Provides functions to initialize the Realtek 8019AS, and send and retreive |
| 17 | * packets |
| 18 | * |
| 19 | * November 15, 2002 - Louis Beaudoin |
| 20 | * processRTL8019Interrupt() - bit mask mistake fixed |
| 21 | * |
| 22 | * September 30, 2002 - Louis Beaudoin |
| 23 | * Receive functions modified to handle errors encountered when receiving a |
| 24 | * fast data stream. Functions now manually retreive data instead of |
| 25 | * using the send packet command. Interface improved by checking for |
| 26 | * overruns and data in the buffer internally. |
| 27 | * Corrected the overrun function - overrun flag was not reset after overrun |
| 28 | * Added support for the Imagecraft Compiler |
| 29 | * Added support to communicate with the NIC using general I/O ports |
| 30 | * |
| 31 | *****************************************************************************/ |
| 32 | |
| 33 | |
| 34 | /***************************************************************************** |
| 35 | * writeRTL( RTL_ADDRESS, RTL_DATA ) |
| 36 | * Args: 1. unsigned char RTL_ADDRESS - register offset of RTL register |
| 37 | * 2. unsigned char RTL_DATA - data to write to register |
| 38 | * Created By: Louis Beaudoin |
| 39 | * Date: September 21, 2002 |
| 40 | * Description: Writes byte to RTL8019 register. |
| 41 | * |
| 42 | * Notes - If using the External SRAM Interface, performs a write to |
| 43 | * address MEMORY_MAPPED_RTL8019_OFFSET + (RTL_ADDRESS<<8) |
| 44 | * The address is sent in the non-multiplxed upper address port so |
| 45 | * no latch is required. |
| 46 | * |
| 47 | * If using general I/O ports, the data port is left in the input |
| 48 | * state with pullups enabled |
| 49 | * |
| 50 | *****************************************************************************/ |
| 51 | #if MEMORY_MAPPED_NIC == 1 |
| 52 | /*#define writeRTL(RTL_ADDRESS,RTL_DATA) do{ *(volatile unsigned char *) \ |
| 53 | (MEMORY_MAPPED_RTL8019_OFFSET \ |
| 54 | + (((unsigned char)(RTL_ADDRESS)) << 8)) = \ |
| 55 | (unsigned char)(RTL_DATA); } while(0)*/ |
| 56 | #define writeRTL nic_write |
| 57 | #else |
| 58 | |
| 59 | |
| 60 | void writeRTL(unsigned char address, unsigned char data) |
| 61 | { |
| 62 | // put the address and data in the port registers - data port is output |
| 63 | outp( address, RTL8019_ADDRESS_PORT ); |
| 64 | outp( 0xFF, RTL8019_DATA_DDR ); |
| 65 | outp( data, RTL8019_DATA_PORT ); |
| 66 | |
| 67 | // toggle write pin |
| 68 | RTL8019_CLEAR_WRITE; |
| 69 | RTL8019_SET_WRITE; |
| 70 | |
| 71 | // set data port back to input with pullups enabled |
| 72 | outp( 0x00, RTL8019_DATA_DDR ); |
| 73 | outp( 0xFF, RTL8019_DATA_PORT ); |
| 74 | } |
| 75 | |
| 76 | |
| 77 | |
| 78 | #endif |
| 79 | |
| 80 | /***************************************************************************** |
| 81 | * readRTL(RTL_ADDRESS) |
| 82 | * Args: unsigned char RTL_ADDRESS - register offset of RTL register |
| 83 | * Created By: Louis Beaudoin |
| 84 | * Date: September 21, 2002 |
| 85 | * Description: Reads byte from RTL8019 register |
| 86 | * |
| 87 | * Notes - If using the External SRAM Interface, performs a read from |
| 88 | * address MEMORY_MAPPED_RTL8019_OFFSET + (RTL_ADDRESS<<8) |
| 89 | * The address is sent in the non-multiplxed upper address port so |
| 90 | * no latch is required. |
| 91 | * |
| 92 | * If using general I/O ports, the data port is assumed to already be |
| 93 | * an input, and is left as an input port when done |
| 94 | * |
| 95 | *****************************************************************************/ |
| 96 | #if MEMORY_MAPPED_NIC == 1 |
| 97 | /*#define readRTL(RTL_ADDRESS) (*(volatile unsigned char *) \ |
| 98 | (MEMORY_MAPPED_RTL8019_OFFSET \ |
| 99 | + (((unsigned char)(RTL_ADDRESS)) << 8)) )*/ |
| 100 | #define readRTL nic_read |
| 101 | #else |
| 102 | |
| 103 | unsigned char readRTL(unsigned char address) |
| 104 | { |
| 105 | unsigned char byte; |
| 106 | |
| 107 | // drive the read address |
| 108 | outp( address, RTL8019_ADDRESS_PORT ); |
| 109 | |
| 110 | //nop(); |
| 111 | |
| 112 | // assert read |
| 113 | RTL8019_CLEAR_READ; |
| 114 | nop(); |
| 115 | |
| 116 | // read in the data |
| 117 | byte = inp( RTL8019_DATA_PIN ); |
| 118 | |
| 119 | // negate read |
| 120 | RTL8019_SET_READ; |
| 121 | |
| 122 | return byte; |
| 123 | } |
| 124 | |
| 125 | #endif |
| 126 | |
| 127 | |
| 128 | |
| 129 | /***************************************************************************** |
| 130 | * RTL8019setupPorts(void); |
| 131 | * |
| 132 | * Created By: Louis Beaudoin |
| 133 | * Date: September 21, 2002 |
| 134 | * Description: Sets up the ports used for communication with the RTL8019 NIC |
| 135 | * (data bus, address bus, read, write, and reset) |
| 136 | *****************************************************************************/ |
| 137 | void RTL8019setupPorts(void) |
| 138 | { |
| 139 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 140 | |
| 141 | #if MEMORY_MAPPED_NIC == 1 |
| 142 | // enable external SRAM interface - no wait states |
| 143 | outp(inp(MCUCR) | (1<<SRE), MCUCR); |
| 144 | |
| 145 | #else |
| 146 | |
| 147 | // make the address port output |
| 148 | outp( 0xFF, RTL8019_ADDRESS_DDR ); |
| 149 | |
| 150 | // make the data port input with pull-ups |
| 151 | outp( 0xFF, RTL8019_DATA_PORT ); |
| 152 | |
| 153 | // make the control port read and write pins outputs and asserted |
| 154 | //outp( inp(RTL8019_CONTROL_DDR) | (1<<RTL8019_CONTROL_READPIN) | |
| 155 | // (1<<RTL8019_CONTROL_WRITEPIN), RTL8019_CONTROL_DDR ); |
| 156 | sbi( RTL8019_CONTROL_DDR, RTL8019_CONTROL_READPIN ); |
| 157 | sbi( RTL8019_CONTROL_DDR, RTL8019_CONTROL_WRITEPIN ); |
| 158 | |
| 159 | //outp( inp(RTL8019_CONTROL_PORT) | (1<<RTL8019_CONTROL_READPIN) | |
| 160 | // (1<<RTL8019_CONTROL_WRITEPIN), RTL8019_CONTROL_PORT ); |
| 161 | sbi( RTL8019_CONTROL_PORT, RTL8019_CONTROL_READPIN ); |
| 162 | sbi( RTL8019_CONTROL_PORT, RTL8019_CONTROL_WRITEPIN ); |
| 163 | |
| 164 | #endif |
| 165 | |
| 166 | // enable output pin for Resetting the RTL8019 |
| 167 | sbi( RTL8019_RESET_DDR, RTL8019_RESET_PIN ); |
| 168 | |
| 169 | |
| 170 | |
| 171 | |
| 172 | |
| 173 | } |
| 174 | |
| 175 | |
| 176 | |
| 177 | /***************************************************************************** |
| 178 | * HARD_RESET_RTL8019() |
| 179 | * |
| 180 | * Created By: Louis Beaudoin |
| 181 | * Date: September 21, 2002 |
| 182 | * Description: Simply toggles the pin that resets the NIC |
| 183 | *****************************************************************************/ |
| 184 | /*#define HARD_RESET_RTL8019() do{ sbi(RTL8019_RESET_PORT, RTL8019_RESET_PIN); \ |
| 185 | Delay_10ms(1); \ |
| 186 | cbi(RTL8019_RESET_PORT, RTL8019_RESET_PIN);} \ |
| 187 | while(0)*/ |
| 188 | |
| 189 | |
| 190 | |
| 191 | /***************************************************************************** |
| 192 | * overrun(void); |
| 193 | * |
| 194 | * Created By: Louis Beaudoin |
| 195 | * Date: September 21, 2002 |
| 196 | * Description: "Canned" receive buffer overrun function originally from |
| 197 | * a National Semiconductor appnote |
| 198 | * Notes: This function must be called before retreiving packets from |
| 199 | * the NIC if there is a buffer overrun |
| 200 | *****************************************************************************/ |
| 201 | void overrun(void); |
| 202 | |
| 203 | |
| 204 | |
| 205 | |
| 206 | //****************************************************************** |
| 207 | //* REALTEK CONTROL REGISTER OFFSETS |
| 208 | //* All offsets in Page 0 unless otherwise specified |
| 209 | //* All functions accessing CR must leave CR in page 0 upon exit |
| 210 | //****************************************************************** |
| 211 | #define CR 0x00 |
| 212 | #define PSTART 0x01 |
| 213 | #define PAR0 0x01 // Page 1 |
| 214 | #define CR9346 0x01 // Page 3 |
| 215 | #define PSTOP 0x02 |
| 216 | #define BNRY 0x03 |
| 217 | #define TSR 0x04 |
| 218 | #define TPSR 0x04 |
| 219 | #define TBCR0 0x05 |
| 220 | #define NCR 0x05 |
| 221 | #define TBCR1 0x06 |
| 222 | #define ISR 0x07 |
| 223 | #define CURR 0x07 // Page 1 |
| 224 | #define RSAR0 0x08 |
| 225 | #define CRDA0 0x08 |
| 226 | #define RSAR1 0x09 |
| 227 | #define CRDA1 0x09 |
| 228 | #define RBCR0 0x0A |
| 229 | #define RBCR1 0x0B |
| 230 | #define RSR 0x0C |
| 231 | #define RCR 0x0C |
| 232 | #define TCR 0x0D |
| 233 | #define CNTR0 0x0D |
| 234 | #define DCR 0x0E |
| 235 | #define CNTR1 0x0E |
| 236 | #define IMR 0x0F |
| 237 | #define CNTR2 0x0F |
| 238 | #define RDMAPORT 0x10 |
| 239 | #define RSTPORT 0x18 |
| 240 | |
| 241 | |
| 242 | /***************************************************************************** |
| 243 | * |
| 244 | * RTL ISR Register Bits |
| 245 | * |
| 246 | *****************************************************************************/ |
| 247 | #define ISR_RST 7 |
| 248 | #define ISR_OVW 4 |
| 249 | #define ISR_PRX 0 |
| 250 | #define ISR_RDC 6 |
| 251 | #define ISR_PTX 1 |
| 252 | |
| 253 | |
| 254 | /***************************************************************************** |
| 255 | * |
| 256 | * RTL Register Initialization Values |
| 257 | * |
| 258 | *****************************************************************************/ |
| 259 | // RCR : accept broadcast packets and packets destined to this MAC |
| 260 | // drop short frames and receive errors |
| 261 | #define RCR_INIT 0x04 |
| 262 | |
| 263 | // TCR : default transmit operation - CRC is generated |
| 264 | #define TCR_INIT 0x00 |
| 265 | |
| 266 | // DCR : allows send packet to be used for packet retreival |
| 267 | // FIFO threshold: 8-bits (works) |
| 268 | // 8-bit transfer mode |
| 269 | #define DCR_INIT 0x58 |
| 270 | |
| 271 | // IMR : interrupt enabled for receive and overrun events |
| 272 | #define IMR_INIT 0x11 |
| 273 | |
| 274 | // buffer boundaries - transmit has 6 256-byte pages |
| 275 | // receive has 26 256-byte pages |
| 276 | // entire available packet buffer space is allocated |
| 277 | #define TXSTART_INIT 0x40 |
| 278 | #define RXSTART_INIT 0x46 |
| 279 | #define RXSTOP_INIT 0x60 |
| 280 | |
| 281 | |
| 282 | |
| 283 | void RTL8019beginPacketSend(unsigned int packetLength) |
| 284 | { |
| 285 | |
| 286 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 287 | unsigned int sendPacketLength; |
| 288 | sendPacketLength = (packetLength>=ETHERNET_MIN_PACKET_LENGTH) ? |
| 289 | packetLength : ETHERNET_MIN_PACKET_LENGTH ; |
| 290 | |
| 291 | //start the NIC |
| 292 | writeRTL(CR,0x22); |
| 293 | |
| 294 | // still transmitting a packet - wait for it to finish |
| 295 | while( readRTL(CR) & 0x04 ); |
| 296 | |
| 297 | //load beginning page for transmit buffer |
| 298 | writeRTL(TPSR,TXSTART_INIT); |
| 299 | |
| 300 | //set start address for remote DMA operation |
| 301 | writeRTL(RSAR0,0x00); |
| 302 | writeRTL(RSAR1,0x40); |
| 303 | |
| 304 | //clear the packet stored interrupt |
| 305 | writeRTL(ISR,(1<<ISR_PTX)); |
| 306 | |
| 307 | //load data byte count for remote DMA |
| 308 | writeRTL(RBCR0, (unsigned char)(packetLength)); |
| 309 | writeRTL(RBCR1, (unsigned char)(packetLength>>8)); |
| 310 | |
| 311 | writeRTL(TBCR0, (unsigned char)(sendPacketLength)); |
| 312 | writeRTL(TBCR1, (unsigned char)((sendPacketLength)>>8)); |
| 313 | |
| 314 | //do remote write operation |
| 315 | writeRTL(CR,0x12); |
| 316 | } |
| 317 | |
| 318 | |
| 319 | |
| 320 | void RTL8019sendPacketData(unsigned char * localBuffer, unsigned int length) |
| 321 | { |
| 322 | unsigned int i; |
| 323 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 324 | for(i=0;i<length;i++) |
| 325 | writeRTL(RDMAPORT, localBuffer[i]); |
| 326 | } |
| 327 | |
| 328 | |
| 329 | |
| 330 | void RTL8019endPacketSend(void) |
| 331 | { |
| 332 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 333 | //send the contents of the transmit buffer onto the network |
| 334 | writeRTL(CR,0x24); |
| 335 | |
| 336 | // clear the remote DMA interrupt |
| 337 | writeRTL(ISR, (1<<ISR_RDC)); |
| 338 | } |
| 339 | |
| 340 | |
| 341 | |
| 342 | |
| 343 | // pointers to locations in the RTL8019 receive buffer |
| 344 | static unsigned char nextPage; |
| 345 | static unsigned int currentRetreiveAddress; |
| 346 | |
| 347 | // location of items in the RTL8019's page header |
| 348 | #define enetpacketstatus 0x00 |
| 349 | #define nextblock_ptr 0x01 |
| 350 | #define enetpacketLenL 0x02 |
| 351 | #define enetpacketLenH 0x03 |
| 352 | |
| 353 | |
| 354 | |
| 355 | unsigned int RTL8019beginPacketRetreive(void) |
| 356 | { |
| 357 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 358 | unsigned char i; |
| 359 | unsigned char bnry; |
| 360 | |
| 361 | unsigned char pageheader[4]; |
| 362 | unsigned int rxlen; |
| 363 | |
| 364 | // check for and handle an overflow |
| 365 | processRTL8019Interrupt(); |
| 366 | |
| 367 | // read CURR from page 1 |
| 368 | writeRTL(CR,0x62); |
| 369 | i = readRTL(CURR); |
| 370 | |
| 371 | // return to page 0 |
| 372 | writeRTL(CR,0x22); |
| 373 | |
| 374 | // read the boundary register - pointing to the beginning of the packet |
| 375 | bnry = readRTL(BNRY) ; |
| 376 | |
| 377 | /* debug_print(PSTR("bnry: ")); |
| 378 | debug_print8(bnry);*/ |
| 379 | |
| 380 | /* debug_print(PSTR("RXSTOP_INIT: ")); |
| 381 | debug_print8(RXSTOP_INIT); |
| 382 | debug_print(PSTR("RXSTART_INIT: ")); |
| 383 | debug_print8(RXSTART_INIT);*/ |
| 384 | // return if there is no packet in the buffer |
| 385 | if( bnry == i ) { |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | |
| 390 | // clear the packet received interrupt flag |
| 391 | writeRTL(ISR, (1<<ISR_PRX)); |
| 392 | |
| 393 | |
| 394 | // the boundary pointer is invalid, reset the contents of the buffer and exit |
| 395 | if( (bnry >= RXSTOP_INIT) || (bnry < RXSTART_INIT) ) |
| 396 | { |
| 397 | writeRTL(BNRY, RXSTART_INIT); |
| 398 | writeRTL(CR, 0x62); |
| 399 | writeRTL(CURR, RXSTART_INIT); |
| 400 | writeRTL(CR, 0x22); |
| 401 | return 0; |
| 402 | } |
| 403 | |
| 404 | // initiate DMA to transfer the RTL8019 packet header |
| 405 | writeRTL(RBCR0, 4); |
| 406 | writeRTL(RBCR1, 0); |
| 407 | writeRTL(RSAR0, 0); |
| 408 | writeRTL(RSAR1, bnry); |
| 409 | writeRTL(CR, 0x0A); |
| 410 | /* debug_print(PSTR("Page header: "));*/ |
| 411 | |
| 412 | for(i=0;i<4;i++) { |
| 413 | pageheader[i] = readRTL(RDMAPORT); |
| 414 | /* debug_print8(pageheader[i]);*/ |
| 415 | } |
| 416 | |
| 417 | // end the DMA operation |
| 418 | writeRTL(CR, 0x22); |
| 419 | for(i = 0; i <= 20; i++) { |
| 420 | if(readRTL(ISR) & 1<<6) { |
| 421 | break; |
| 422 | } |
| 423 | } |
| 424 | writeRTL(ISR, 1<<6); |
| 425 | |
| 426 | |
| 427 | |
| 428 | rxlen = (pageheader[enetpacketLenH]<<8) + pageheader[enetpacketLenL]; |
| 429 | nextPage = pageheader[nextblock_ptr] ; |
| 430 | |
| 431 | currentRetreiveAddress = (bnry<<8) + 4; |
| 432 | |
| 433 | /* debug_print(PSTR("nextPage: ")); |
| 434 | debug_print8(nextPage);*/ |
| 435 | |
| 436 | // if the nextPage pointer is invalid, the packet is not ready yet - exit |
| 437 | if( (nextPage >= RXSTOP_INIT) || (nextPage < RXSTART_INIT) ) { |
| 438 | /* UDR0 = '0';*/ |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | return rxlen-4; |
| 443 | } |
| 444 | |
| 445 | |
| 446 | void RTL8019retreivePacketData(unsigned char * localBuffer, unsigned int length) |
| 447 | { |
| 448 | unsigned int i; |
| 449 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 450 | // initiate DMA to transfer the data |
| 451 | writeRTL(RBCR0, (unsigned char)length); |
| 452 | writeRTL(RBCR1, (unsigned char)(length>>8)); |
| 453 | writeRTL(RSAR0, (unsigned char)currentRetreiveAddress); |
| 454 | writeRTL(RSAR1, (unsigned char)(currentRetreiveAddress>>8)); |
| 455 | writeRTL(CR, 0x0A); |
| 456 | for(i=0;i<length;i++) |
| 457 | localBuffer[i] = readRTL(RDMAPORT); |
| 458 | |
| 459 | // end the DMA operation |
| 460 | writeRTL(CR, 0x22); |
| 461 | for(i = 0; i <= 20; i++) |
| 462 | if(readRTL(ISR) & 1<<6) |
| 463 | break; |
| 464 | writeRTL(ISR, 1<<6); |
| 465 | |
| 466 | currentRetreiveAddress += length; |
| 467 | if( currentRetreiveAddress >= 0x6000 ) |
| 468 | currentRetreiveAddress = currentRetreiveAddress - (0x6000-0x4600) ; |
| 469 | } |
| 470 | |
| 471 | |
| 472 | |
| 473 | void RTL8019endPacketRetreive(void) |
| 474 | { |
| 475 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 476 | unsigned char i; |
| 477 | |
| 478 | // end the DMA operation |
| 479 | writeRTL(CR, 0x22); |
| 480 | for(i = 0; i <= 20; i++) |
| 481 | if(readRTL(ISR) & 1<<6) |
| 482 | break; |
| 483 | writeRTL(ISR, 1<<6); |
| 484 | |
| 485 | // set the boundary register to point to the start of the next packet |
| 486 | writeRTL(BNRY, nextPage); |
| 487 | } |
| 488 | |
| 489 | |
| 490 | void overrun(void) |
| 491 | { |
| 492 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 493 | unsigned char data_L, resend; |
| 494 | |
| 495 | data_L = readRTL(CR); |
| 496 | writeRTL(CR, 0x21); |
| 497 | Delay_1ms(2); |
| 498 | writeRTL(RBCR0, 0x00); |
| 499 | writeRTL(RBCR1, 0x00); |
| 500 | if(!(data_L & 0x04)) |
| 501 | resend = 0; |
| 502 | else if(data_L & 0x04) |
| 503 | { |
| 504 | data_L = readRTL(ISR); |
| 505 | if((data_L & 0x02) || (data_L & 0x08)) |
| 506 | resend = 0; |
| 507 | else |
| 508 | resend = 1; |
| 509 | } |
| 510 | |
| 511 | writeRTL(TCR, 0x02); |
| 512 | writeRTL(CR, 0x22); |
| 513 | writeRTL(BNRY, RXSTART_INIT); |
| 514 | writeRTL(CR, 0x62); |
| 515 | writeRTL(CURR, RXSTART_INIT); |
| 516 | writeRTL(CR, 0x22); |
| 517 | writeRTL(ISR, 0x10); |
| 518 | writeRTL(TCR, TCR_INIT); |
| 519 | |
| 520 | writeRTL(ISR, 0xFF); |
| 521 | } |
| 522 | |
| 523 | |
| 524 | |
| 525 | |
| 526 | /*! |
| 527 | * \brief Size of a single ring buffer page. |
| 528 | */ |
| 529 | #define NIC_PAGE_SIZE 0x100 |
| 530 | |
| 531 | /*! |
| 532 | * \brief First ring buffer page address. |
| 533 | */ |
| 534 | #define NIC_START_PAGE 0x40 |
| 535 | |
| 536 | /*! |
| 537 | * \brief Last ring buffer page address plus 1. |
| 538 | */ |
| 539 | #define NIC_STOP_PAGE 0x60 |
| 540 | |
| 541 | /*! |
| 542 | * \brief Number of pages in a single transmit buffer. |
| 543 | * |
| 544 | * This should be at least the MTU size. |
| 545 | */ |
| 546 | #define NIC_TX_PAGES 6 |
| 547 | |
| 548 | /*! |
| 549 | * \brief Number of transmit buffers. |
| 550 | */ |
| 551 | #define NIC_TX_BUFFERS 2 |
| 552 | |
| 553 | /*! |
| 554 | * \brief Controller memory layout: |
| 555 | * |
| 556 | * 0x4000 - 0x4bff 3k bytes transmit buffer |
| 557 | * 0x4c00 - 0x5fff 5k bytes receive buffer |
| 558 | */ |
| 559 | #define NIC_FIRST_TX_PAGE NIC_START_PAGE |
| 560 | #define NIC_FIRST_RX_PAGE (NIC_FIRST_TX_PAGE + NIC_TX_PAGES * NIC_TX_BUFFERS) |
| 561 | |
| 562 | /*! |
| 563 | * \brief Standard sizing information |
| 564 | */ |
| 565 | #define TX_PAGES 12 /* Allow for 2 back-to-back frames */ |
| 566 | |
adamdunkels | d311bf1 | 2004-07-04 20:17:37 +0000 | [diff] [blame] | 567 | static unsigned char mac[6] = {0x00,0x06,0x98,0x01,0x02,0x29}; |
adamdunkels | 3023dee | 2003-07-04 10:54:51 +0000 | [diff] [blame] | 568 | void Delay(long nops) |
| 569 | { |
| 570 | volatile long i; |
| 571 | |
| 572 | for(i = 0; i < nops; i++) |
| 573 | #ifdef __IMAGECRAFT__ |
| 574 | asm("nop\n"); |
| 575 | #else |
| 576 | asm volatile("nop\n\t"::); |
| 577 | #endif |
| 578 | } |
| 579 | |
| 580 | static int NicReset(void) |
| 581 | { |
| 582 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 583 | unsigned char i; |
| 584 | unsigned char j; |
| 585 | |
| 586 | for(j = 0; j < 20; j++) { |
| 587 | debug_print(PSTR("SW-Reset...")); |
| 588 | i = nic_read(NIC_RESET); |
| 589 | Delay(500); |
| 590 | nic_write(NIC_RESET, i); |
| 591 | for(i = 0; i < 20; i++) { |
| 592 | Delay(5000); |
| 593 | |
| 594 | /* |
| 595 | * ID detection added for version 1.1 boards. |
| 596 | */ |
| 597 | if((nic_read(NIC_PG0_ISR) & NIC_ISR_RST) != 0 && |
| 598 | nic_read(NIC_PG0_RBCR0) == 0x50 && |
| 599 | nic_read(NIC_PG0_RBCR1) == 0x70) { |
| 600 | debug_print(PSTR("OK\r\n")); |
| 601 | return 0; |
| 602 | } |
| 603 | } |
| 604 | debug_print(PSTR("failed\r\n\x07")); |
| 605 | |
| 606 | /* |
| 607 | * Toggle the hardware reset line. Since Ethernut version 1.3 the |
| 608 | * hardware reset pin of the nic is no longer connected to bit 4 |
| 609 | * on port E, but wired to the board reset line. |
| 610 | */ |
| 611 | if(j == 10) { |
| 612 | debug_print(PSTR("Ethernut 1.1 HW-Reset\r\n")); |
| 613 | sbi(DDRE, 4); |
| 614 | sbi(PORTE, 4); |
| 615 | Delay(100000); |
| 616 | cbi(PORTE, 4); |
| 617 | Delay(250000); |
| 618 | } |
| 619 | } |
| 620 | return -1; |
| 621 | } |
| 622 | |
| 623 | void initRTL8019(void) |
| 624 | { |
| 625 | unsigned char i, rb; |
| 626 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 627 | |
| 628 | RTL8019setupPorts(); |
| 629 | |
| 630 | /*#define nic_write writeRTL |
| 631 | #define nic_read readRTL*/ |
| 632 | /* |
| 633 | * Disable NIC interrupts. |
| 634 | */ |
| 635 | cbi(EIMSK, INT5); |
| 636 | |
| 637 | /* if(NicReset(base)) |
| 638 | return -1;*/ |
| 639 | #if 0 |
| 640 | /* |
| 641 | * Mask all interrupts and clear any interrupt status flag to set the |
| 642 | * INT pin back to low. |
| 643 | */ |
| 644 | nic_write(NIC_PG0_IMR, 0); |
| 645 | nic_write(NIC_PG0_ISR, 0xff); |
| 646 | |
| 647 | /* |
| 648 | * During reset the nic loaded its initial configuration from an |
| 649 | * external eeprom. On the ethernut board we do not have any |
| 650 | * configuration eeprom, but simply tied the eeprom data line to |
| 651 | * high level. So we have to clear some bits in the configuration |
| 652 | * register. Switch to register page 3. |
| 653 | */ |
| 654 | nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2 | NIC_CR_PS0 | NIC_CR_PS1); |
| 655 | |
| 656 | /* |
| 657 | * The nic configuration registers are write protected unless both |
| 658 | * EEM bits are set to 1. |
| 659 | */ |
| 660 | nic_write(NIC_PG3_EECR, NIC_EECR_EEM0 | NIC_EECR_EEM1); |
| 661 | |
| 662 | /* |
| 663 | * Disable sleep and power down. |
| 664 | */ |
| 665 | nic_write(NIC_PG3_CONFIG3, 0); |
| 666 | |
| 667 | /* |
| 668 | * Network media had been set to 10Base2 by the virtual EEPROM and |
| 669 | * will be set now to auto detect. This will initiate a link test. |
| 670 | * We don't force 10BaseT, because this would disable the link test. |
| 671 | */ |
| 672 | nic_write(NIC_PG3_CONFIG2, NIC_CONFIG2_BSELB); |
| 673 | |
| 674 | /* |
| 675 | * Reenable write protection of the nic configuration registers |
| 676 | * and wait for link test to complete. |
| 677 | */ |
| 678 | nic_write(NIC_PG3_EECR, 0); |
| 679 | /* NutSleep(WAIT500);*/ |
| 680 | Delay_10ms(50); |
| 681 | |
| 682 | /* |
| 683 | * Switch to register page 0 and set data configuration register |
| 684 | * to byte-wide DMA transfers, normal operation (no loopback), |
| 685 | * send command not executed and 8 byte fifo threshold. |
| 686 | */ |
| 687 | nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2); |
| 688 | nic_write(NIC_PG0_DCR, NIC_DCR_LS | NIC_DCR_FT1); |
| 689 | |
| 690 | /* |
| 691 | * Clear remote dma byte count register. |
| 692 | */ |
| 693 | nic_write(NIC_PG0_RBCR0, 0); |
| 694 | nic_write(NIC_PG0_RBCR1, 0); |
| 695 | |
| 696 | /* |
| 697 | * Temporarily set receiver to monitor mode and transmitter to |
| 698 | * internal loopback mode. Incoming packets will not be stored |
| 699 | * in the nic ring buffer and no data will be send to the network. |
| 700 | */ |
| 701 | nic_write(NIC_PG0_RCR, NIC_RCR_MON); |
| 702 | nic_write(NIC_PG0_TCR, NIC_TCR_LB0); |
| 703 | |
| 704 | /* |
| 705 | * Configure the nic's ring buffer page layout. |
| 706 | * NIC_PG0_BNRY: Last page read. |
| 707 | * NIC_PG0_PSTART: First page of receiver buffer. |
| 708 | * NIC_PG0_PSTOP: Last page of receiver buffer. |
| 709 | */ |
| 710 | nic_write(NIC_PG0_TPSR, NIC_FIRST_TX_PAGE); |
| 711 | nic_write(NIC_PG0_BNRY, NIC_STOP_PAGE - 1); |
| 712 | nic_write(NIC_PG0_PSTART, NIC_FIRST_RX_PAGE); |
| 713 | nic_write(NIC_PG0_PSTOP, NIC_STOP_PAGE); |
| 714 | |
| 715 | /* |
| 716 | * Once again clear interrupt status register. |
| 717 | */ |
| 718 | nic_write(NIC_PG0_ISR, 0xff); |
| 719 | |
| 720 | /* |
| 721 | * Switch to register page 1 and copy our MAC address into the nic. |
| 722 | * We are still in stop mode. |
| 723 | */ |
| 724 | nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2 | NIC_CR_PS0); |
| 725 | for(i = 0; i < 6; i++) |
| 726 | nic_write(NIC_PG1_PAR0 + i, mac[i]); |
| 727 | |
| 728 | /* |
| 729 | * Clear multicast filter bits to disable all packets. |
| 730 | */ |
| 731 | for(i = 0; i < 8; i++) |
| 732 | nic_write(NIC_PG1_MAR0 + i, 0); |
| 733 | |
| 734 | /* |
| 735 | * Set current page pointer to one page after the boundary pointer. |
| 736 | */ |
| 737 | nic_write(NIC_PG1_CURR, NIC_START_PAGE + TX_PAGES); |
| 738 | |
| 739 | /* |
| 740 | * Switch back to register page 0, remaining in stop mode. |
| 741 | */ |
| 742 | nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2); |
| 743 | |
| 744 | /* |
| 745 | * Take receiver out of monitor mode and enable it for accepting |
| 746 | * broadcasts. |
| 747 | */ |
| 748 | nic_write(NIC_PG0_RCR, NIC_RCR_AB); |
| 749 | |
| 750 | /* |
| 751 | * Clear all interrupt status flags and enable interrupts. |
| 752 | */ |
| 753 | nic_write(NIC_PG0_ISR, 0xff); |
| 754 | nic_write(NIC_PG0_IMR, NIC_IMR_PRXE | NIC_IMR_PTXE | NIC_IMR_RXEE | |
| 755 | NIC_IMR_TXEE | NIC_IMR_OVWE); |
| 756 | |
| 757 | /* |
| 758 | * Fire up the nic by clearing the stop bit and setting the start bit. |
| 759 | * To activate the local receive dma we must also take the nic out of |
| 760 | * the local loopback mode. |
| 761 | */ |
| 762 | nic_write(NIC_CR, NIC_CR_STA | NIC_CR_RD2); |
| 763 | nic_write(NIC_PG0_TCR, 0); |
| 764 | |
| 765 | /* NutSleep(WAIT500);*/ |
| 766 | Delay_10ms(50); |
| 767 | |
| 768 | |
| 769 | #endif /* 0 */ |
| 770 | |
| 771 | NicReset(); |
| 772 | |
| 773 | debug_print(PSTR("Init controller...")); |
| 774 | nic_write(NIC_PG0_IMR, 0); |
| 775 | nic_write(NIC_PG0_ISR, 0xff); |
| 776 | nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2 | NIC_CR_PS0 | NIC_CR_PS1); |
| 777 | nic_write(NIC_PG3_EECR, NIC_EECR_EEM0 | NIC_EECR_EEM1); |
| 778 | nic_write(NIC_PG3_CONFIG3, 0); |
| 779 | nic_write(NIC_PG3_CONFIG2, NIC_CONFIG2_BSELB); |
| 780 | nic_write(NIC_PG3_EECR, 0); |
| 781 | /* Delay(50000);*/ |
| 782 | Delay_10ms(200); |
| 783 | nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2); |
| 784 | nic_write(NIC_PG0_DCR, NIC_DCR_LS | NIC_DCR_FT1); |
| 785 | nic_write(NIC_PG0_RBCR0, 0); |
| 786 | nic_write(NIC_PG0_RBCR1, 0); |
| 787 | nic_write(NIC_PG0_RCR, NIC_RCR_MON); |
| 788 | nic_write(NIC_PG0_TCR, NIC_TCR_LB0); |
| 789 | nic_write(NIC_PG0_TPSR, NIC_FIRST_TX_PAGE); |
| 790 | nic_write(NIC_PG0_BNRY, NIC_STOP_PAGE - 1); |
| 791 | nic_write(NIC_PG0_PSTART, NIC_FIRST_RX_PAGE); |
| 792 | nic_write(NIC_PG0_PSTOP, NIC_STOP_PAGE); |
| 793 | nic_write(NIC_PG0_ISR, 0xff); |
| 794 | nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2 | NIC_CR_PS0); |
| 795 | for(i = 0; i < 6; i++) |
| 796 | nic_write(NIC_PG1_PAR0 + i, mac[i]); |
| 797 | for(i = 0; i < 8; i++) |
| 798 | nic_write(NIC_PG1_MAR0 + i, 0); |
| 799 | nic_write(NIC_PG1_CURR, NIC_START_PAGE + TX_PAGES); |
| 800 | nic_write(NIC_CR, NIC_CR_STP | NIC_CR_RD2); |
| 801 | nic_write(NIC_PG0_RCR, NIC_RCR_AB); |
| 802 | nic_write(NIC_PG0_ISR, 0xff); |
| 803 | nic_write(NIC_PG0_IMR, 0); |
| 804 | nic_write(NIC_CR, NIC_CR_STA | NIC_CR_RD2); |
| 805 | nic_write(NIC_PG0_TCR, 0); |
| 806 | /* Delay(1000000)*/ |
| 807 | Delay_10ms(200); |
| 808 | |
| 809 | |
| 810 | nic_write(NIC_CR, NIC_CR_STA | NIC_CR_RD2 | NIC_CR_PS0 | NIC_CR_PS1); |
| 811 | rb = nic_read(NIC_PG3_CONFIG0); |
| 812 | debug_print8(rb); |
| 813 | switch(rb & 0xC0) { |
| 814 | case 0x00: |
| 815 | debug_print(PSTR("RTL8019AS ")); |
| 816 | if(rb & 0x08) |
| 817 | debug_print(PSTR("jumper mode: ")); |
| 818 | if(rb & 0x20) |
| 819 | debug_print(PSTR("AUI ")); |
| 820 | if(rb & 0x10) |
| 821 | debug_print(PSTR("PNP ")); |
| 822 | break; |
| 823 | case 0xC0: |
| 824 | debug_print(PSTR("RTL8019 ")); |
| 825 | if(rb & 0x08) |
| 826 | debug_print(PSTR("jumper mode: ")); |
| 827 | break; |
| 828 | default: |
| 829 | debug_print(PSTR("Unknown chip ")); |
| 830 | debug_print8(rb); |
| 831 | break; |
| 832 | } |
| 833 | if(rb & 0x04) |
| 834 | debug_print(PSTR("BNC\x07 ")); |
| 835 | if(rb & 0x03) |
| 836 | debug_print(PSTR("Failed\x07 ")); |
| 837 | |
| 838 | /* rb = nic_read(NIC_PG3_CONFIG1); |
| 839 | debug_print8(rb);*/ |
| 840 | /* NutPrintFormat(0, "IRQ%u ", (rb >> 4) & 7);*/ |
| 841 | /* debug_print("IRQ "); |
| 842 | debug_print8((rb >> 4) & 7);*/ |
| 843 | |
| 844 | rb = nic_read(NIC_PG3_CONFIG2); |
| 845 | debug_print8(rb); |
| 846 | switch(rb & 0xC0) { |
| 847 | case 0x00: |
| 848 | debug_print(PSTR("Auto ")); |
| 849 | break; |
| 850 | case 0x40: |
| 851 | debug_print(PSTR("10BaseT ")); |
| 852 | break; |
| 853 | case 0x80: |
| 854 | debug_print(PSTR("10Base5 ")); |
| 855 | break; |
| 856 | case 0xC0: |
| 857 | debug_print(PSTR("10Base2 ")); |
| 858 | break; |
| 859 | } |
| 860 | |
| 861 | |
| 862 | return; |
| 863 | |
| 864 | /* HARD_RESET_RTL8019();*/ |
| 865 | |
| 866 | // do soft reset |
| 867 | writeRTL( ISR, readRTL(ISR) ) ; |
| 868 | Delay_10ms(5); |
| 869 | |
| 870 | writeRTL(CR,0x21); // stop the NIC, abort DMA, page 0 |
| 871 | Delay_1ms(2); // make sure nothing is coming in or going out |
| 872 | writeRTL(DCR, DCR_INIT); // 0x58 |
| 873 | writeRTL(RBCR0,0x00); |
| 874 | writeRTL(RBCR1,0x00); |
| 875 | writeRTL(RCR,0x04); |
| 876 | writeRTL(TPSR, TXSTART_INIT); |
| 877 | writeRTL(TCR,0x02); |
| 878 | writeRTL(PSTART, RXSTART_INIT); |
| 879 | writeRTL(BNRY, RXSTART_INIT); |
| 880 | writeRTL(PSTOP, RXSTOP_INIT); |
| 881 | writeRTL(CR, 0x61); |
| 882 | Delay_1ms(2); |
| 883 | writeRTL(CURR, RXSTART_INIT); |
| 884 | |
| 885 | writeRTL(PAR0+0, MYMAC_0); |
| 886 | writeRTL(PAR0+1, MYMAC_1); |
| 887 | writeRTL(PAR0+2, MYMAC_2); |
| 888 | writeRTL(PAR0+3, MYMAC_3); |
| 889 | writeRTL(PAR0+4, MYMAC_4); |
| 890 | writeRTL(PAR0+5, MYMAC_5); |
| 891 | |
| 892 | writeRTL(CR,0x21); |
| 893 | writeRTL(DCR, DCR_INIT); |
| 894 | writeRTL(CR,0x22); |
| 895 | writeRTL(ISR,0xFF); |
| 896 | writeRTL(IMR, IMR_INIT); |
| 897 | writeRTL(TCR, TCR_INIT); |
| 898 | |
| 899 | writeRTL(CR, 0x22); // start the NIC |
| 900 | } |
| 901 | |
| 902 | |
| 903 | void processRTL8019Interrupt(void) |
| 904 | { |
| 905 | volatile unsigned char *base = (unsigned char *)0x8300; |
| 906 | unsigned char byte = readRTL(ISR); |
| 907 | |
| 908 | if( byte & (1<<ISR_OVW) ) |
| 909 | overrun(); |
| 910 | |
| 911 | } |
| 912 | |
| 913 | /* |
| 914 | unsigned char RTL8019ReceiveEmpty(void) |
| 915 | { |
| 916 | unsigned char temp; |
| 917 | |
| 918 | // read CURR from page 1 |
| 919 | writeRTL(CR,0x62); |
| 920 | temp = readRTL(CURR); |
| 921 | |
| 922 | // return to page 0 |
| 923 | writeRTL(CR,0x22); |
| 924 | |
| 925 | return ( readRTL(BNRY) == temp ); |
| 926 | |
| 927 | }*/ |
| 928 | |
| 929 | |
| 930 | |
| 931 | |