1 | /* Name: usbdrvasm15.inc
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2 | * Project: AVR USB driver
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3 | * Author: contributed by V. Bosch
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4 | * Creation Date: 2007-08-06
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5 | * Tabsize: 4
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6 | * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
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7 | * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
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8 | * Revision: $Id: usbdrvasm15.inc 692 2008-11-07 15:07:40Z cs $
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9 | */
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10 |
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11 | /* Do not link this file! Link usbdrvasm.S instead, which includes the
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12 | * appropriate implementation!
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13 | */
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14 |
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15 | /*
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16 | General Description:
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17 | This file is the 15 MHz version of the asssembler part of the USB driver. It
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18 | requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC
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19 | oscillator).
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20 |
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21 | See usbdrv.h for a description of the entire driver.
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22 |
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23 | Since almost all of this code is timing critical, don't change unless you
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24 | really know what you are doing! Many parts require not only a maximum number
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25 | of CPU cycles, but even an exact number of cycles!
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26 | */
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27 |
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28 | ;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
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29 | ;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte
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30 | ; Numbers in brackets are clocks counted from center of last sync bit
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31 | ; when instruction starts
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32 |
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33 | ;----------------------------------------------------------------------------
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34 | ; order of registers pushed:
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35 | ; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4
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36 | ;----------------------------------------------------------------------------
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37 | USB_INTR_VECTOR:
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38 | push YL ;2 push only what is necessary to sync with edge ASAP
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39 | in YL, SREG ;1
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40 | push YL ;2
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41 | ;----------------------------------------------------------------------------
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42 | ; Synchronize with sync pattern:
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43 | ;
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44 | ; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
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45 | ; sync up with J to K edge during sync pattern -- use fastest possible loops
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46 | ;The first part waits at most 1 bit long since we must be in sync pattern.
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47 | ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
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48 | ;waitForJ, ensure that this prerequisite is met.
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49 | waitForJ:
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50 | inc YL
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51 | sbis USBIN, USBMINUS
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52 | brne waitForJ ; just make sure we have ANY timeout
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53 | ;-------------------------------------------------------------------------------
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54 | ; The following code results in a sampling window of < 1/4 bit
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55 | ; which meets the spec.
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56 | ;-------------------------------------------------------------------------------
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57 | waitForK: ;-
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58 | sbis USBIN, USBMINUS ;1 [00] <-- sample
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59 | rjmp foundK ;2 [01]
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60 | sbis USBIN, USBMINUS ; <-- sample
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61 | rjmp foundK
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62 | sbis USBIN, USBMINUS ; <-- sample
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63 | rjmp foundK
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64 | sbis USBIN, USBMINUS ; <-- sample
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65 | rjmp foundK
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66 | sbis USBIN, USBMINUS ; <-- sample
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67 | rjmp foundK
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68 | sbis USBIN, USBMINUS ; <-- sample
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69 | rjmp foundK
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70 | #if USB_COUNT_SOF
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71 | lds YL, usbSofCount
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72 | inc YL
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73 | sts usbSofCount, YL
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74 | #endif /* USB_COUNT_SOF */
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75 | #ifdef USB_SOF_HOOK
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76 | USB_SOF_HOOK
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77 | #endif
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78 | rjmp sofError
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79 | ;------------------------------------------------------------------------------
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80 | ; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for
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81 | ; center sampling]
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82 | ; we have 1 bit time for setup purposes, then sample again.
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83 | ; Numbers in brackets are cycles from center of first sync (double K)
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84 | ; bit after the instruction
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85 | ;------------------------------------------------------------------------------
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86 | foundK: ;- [02]
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87 | lds YL, usbInputBufOffset;2 [03+04] tx loop
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88 | push YH ;2 [05+06]
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89 | clr YH ;1 [07]
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90 | subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init]
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91 | sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init]
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92 | push shift ;2 [10+11]
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93 | ser shift ;1 [12]
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94 | sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early)
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95 | rjmp haveTwoBitsK ;2 [00] [14]
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96 | pop shift ;2 [15+16] undo the push from before
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97 | pop YH ;2 [17+18] undo the push from before
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98 | rjmp waitForK ;2 [19+20] this was not the end of sync, retry
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99 | ; The entire loop from waitForK until rjmp waitForK above must not exceed two
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100 | ; bit times (= 20 cycles).
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101 |
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102 | ;----------------------------------------------------------------------------
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103 | ; push more registers and initialize values while we sample the first bits:
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104 | ;----------------------------------------------------------------------------
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105 | haveTwoBitsK: ;- [01]
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106 | push x1 ;2 [02+03]
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107 | push x2 ;2 [04+05]
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108 | push x3 ;2 [06+07]
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109 | push bitcnt ;2 [08+09]
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110 | in x1, USBIN ;1 [00] [10] <-- sample bit 0
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111 | bst x1, USBMINUS ;1 [01]
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112 | bld shift, 0 ;1 [02]
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113 | push cnt ;2 [03+04]
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114 | ldi cnt, USB_BUFSIZE ;1 [05]
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115 | push x4 ;2 [06+07] tx loop
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116 | rjmp rxLoop ;2 [08]
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117 | ;----------------------------------------------------------------------------
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118 | ; Receiver loop (numbers in brackets are cycles within byte after instr)
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119 | ;----------------------------------------------------------------------------
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120 | unstuff0: ;- [07] (branch taken)
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121 | andi x3, ~0x01 ;1 [08]
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122 | mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit
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123 | in x2, USBIN ;1 [00] [10] <-- sample bit 1 again
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124 | andi x2, USBMASK ;1 [01]
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125 | breq se0Hop ;1 [02] SE0 check for bit 1
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126 | ori shift, 0x01 ;1 [03] 0b00000001
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127 | nop ;1 [04]
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128 | rjmp didUnstuff0 ;2 [05]
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129 | ;-----------------------------------------------------
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130 | unstuff1: ;- [05] (branch taken)
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131 | mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit
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132 | andi x3, ~0x02 ;1 [07]
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133 | ori shift, 0x02 ;1 [08] 0b00000010
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134 | nop ;1 [09]
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135 | in x1, USBIN ;1 [00] [10] <-- sample bit 2 again
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136 | andi x1, USBMASK ;1 [01]
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137 | breq se0Hop ;1 [02] SE0 check for bit 2
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138 | rjmp didUnstuff1 ;2 [03]
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139 | ;-----------------------------------------------------
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140 | unstuff2: ;- [05] (branch taken)
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141 | andi x3, ~0x04 ;1 [06]
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142 | ori shift, 0x04 ;1 [07] 0b00000100
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143 | mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit
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144 | nop ;1 [09]
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145 | in x2, USBIN ;1 [00] [10] <-- sample bit 3
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146 | andi x2, USBMASK ;1 [01]
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147 | breq se0Hop ;1 [02] SE0 check for bit 3
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148 | rjmp didUnstuff2 ;2 [03]
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149 | ;-----------------------------------------------------
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150 | unstuff3: ;- [00] [10] (branch taken)
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151 | in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late
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152 | andi x2, USBMASK ;1 [02]
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153 | breq se0Hop ;1 [03] SE0 check for stuffed bit 3
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154 | andi x3, ~0x08 ;1 [04]
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155 | ori shift, 0x08 ;1 [05] 0b00001000
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156 | rjmp didUnstuff3 ;2 [06]
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157 | ;----------------------------------------------------------------------------
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158 | ; extra jobs done during bit interval:
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159 | ;
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160 | ; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs],
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161 | ; overflow check, jump to the head of rxLoop
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162 | ; bit 1: SE0 check
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163 | ; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long]
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164 | ; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long]
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165 | ; bit 4: SE0 check, none
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166 | ; bit 5: SE0 check, none
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167 | ; bit 6: SE0 check, none
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168 | ; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others
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169 | ;----------------------------------------------------------------------------
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170 | rxLoop: ;- [09]
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171 | in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed)
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172 | andi x2, USBMASK ;1 [01]
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173 | brne SkipSe0Hop ;1 [02]
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174 | se0Hop: ;- [02]
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175 | rjmp se0 ;2 [03] SE0 check for bit 1
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176 | SkipSe0Hop: ;- [03]
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177 | ser x3 ;1 [04]
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178 | andi shift, 0xf9 ;1 [05] 0b11111001
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179 | breq unstuff0 ;1 [06]
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180 | didUnstuff0: ;- [06]
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181 | eor x1, x2 ;1 [07]
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182 | bst x1, USBMINUS ;1 [08]
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183 | bld shift, 1 ;1 [09]
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184 | in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed)
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185 | andi x1, USBMASK ;1 [01]
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186 | breq se0Hop ;1 [02] SE0 check for bit 2
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187 | andi shift, 0xf3 ;1 [03] 0b11110011
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188 | breq unstuff1 ;1 [04] do remaining work for bit 1
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189 | didUnstuff1: ;- [04]
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190 | eor x2, x1 ;1 [05]
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191 | bst x2, USBMINUS ;1 [06]
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192 | bld shift, 2 ;1 [07]
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193 | nop2 ;2 [08+09]
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194 | in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed)
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195 | andi x2, USBMASK ;1 [01]
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196 | breq se0Hop ;1 [02] SE0 check for bit 3
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197 | andi shift, 0xe7 ;1 [03] 0b11100111
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198 | breq unstuff2 ;1 [04]
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199 | didUnstuff2: ;- [04]
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200 | eor x1, x2 ;1 [05]
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201 | bst x1, USBMINUS ;1 [06]
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202 | bld shift, 3 ;1 [07]
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203 | didUnstuff3: ;- [07]
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204 | andi shift, 0xcf ;1 [08] 0b11001111
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205 | breq unstuff3 ;1 [09]
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206 | in x1, USBIN ;1 [00] [10] <-- sample bit 4
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207 | andi x1, USBMASK ;1 [01]
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208 | breq se0Hop ;1 [02] SE0 check for bit 4
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209 | eor x2, x1 ;1 [03]
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210 | bst x2, USBMINUS ;1 [04]
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211 | bld shift, 4 ;1 [05]
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212 | didUnstuff4: ;- [05]
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213 | andi shift, 0x9f ;1 [06] 0b10011111
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214 | breq unstuff4 ;1 [07]
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215 | nop2 ;2 [08+09]
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216 | in x2, USBIN ;1 [00] [10] <-- sample bit 5
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217 | andi x2, USBMASK ;1 [01]
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218 | breq se0 ;1 [02] SE0 check for bit 5
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219 | eor x1, x2 ;1 [03]
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220 | bst x1, USBMINUS ;1 [04]
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221 | bld shift, 5 ;1 [05]
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222 | didUnstuff5: ;- [05]
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223 | andi shift, 0x3f ;1 [06] 0b00111111
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224 | breq unstuff5 ;1 [07]
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225 | nop2 ;2 [08+09]
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226 | in x1, USBIN ;1 [00] [10] <-- sample bit 6
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227 | andi x1, USBMASK ;1 [01]
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228 | breq se0 ;1 [02] SE0 check for bit 6
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229 | eor x2, x1 ;1 [03]
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230 | bst x2, USBMINUS ;1 [04]
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231 | bld shift, 6 ;1 [05]
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232 | didUnstuff6: ;- [05]
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233 | cpi shift, 0x02 ;1 [06] 0b00000010
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234 | brlo unstuff6 ;1 [07]
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235 | nop2 ;2 [08+09]
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236 | in x2, USBIN ;1 [00] [10] <-- sample bit 7
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237 | andi x2, USBMASK ;1 [01]
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238 | breq se0 ;1 [02] SE0 check for bit 7
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239 | eor x1, x2 ;1 [03]
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240 | bst x1, USBMINUS ;1 [04]
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241 | bld shift, 7 ;1 [05]
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242 | didUnstuff7: ;- [05]
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243 | cpi shift, 0x04 ;1 [06] 0b00000100
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244 | brlo unstuff7 ;1 [07]
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245 | eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others
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246 | nop ;1 [09]
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247 | in x1, USBIN ;1 [00] [10] <-- sample bit 0
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248 | st y+, x3 ;2 [01+02] store data
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249 | eor x2, x1 ;1 [03]
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250 | bst x2, USBMINUS ;1 [04]
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251 | bld shift, 0 ;1 [05]
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252 | subi cnt, 1 ;1 [06]
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253 | brcs overflow ;1 [07]
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254 | rjmp rxLoop ;2 [08]
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255 | ;-----------------------------------------------------
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256 | unstuff4: ;- [08]
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257 | andi x3, ~0x10 ;1 [09]
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258 | in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4
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259 | andi x1, USBMASK ;1 [01]
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260 | breq se0 ;1 [02] SE0 check for stuffed bit 4
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261 | ori shift, 0x10 ;1 [03]
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262 | rjmp didUnstuff4 ;2 [04]
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263 | ;-----------------------------------------------------
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264 | unstuff5: ;- [08]
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265 | ori shift, 0x20 ;1 [09]
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266 | in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5
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267 | andi x2, USBMASK ;1 [01]
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268 | breq se0 ;1 [02] SE0 check for stuffed bit 5
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269 | andi x3, ~0x20 ;1 [03]
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270 | rjmp didUnstuff5 ;2 [04]
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271 | ;-----------------------------------------------------
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272 | unstuff6: ;- [08]
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273 | andi x3, ~0x40 ;1 [09]
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274 | in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6
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275 | andi x1, USBMASK ;1 [01]
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276 | breq se0 ;1 [02] SE0 check for stuffed bit 6
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277 | ori shift, 0x40 ;1 [03]
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278 | rjmp didUnstuff6 ;2 [04]
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279 | ;-----------------------------------------------------
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280 | unstuff7: ;- [08]
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281 | andi x3, ~0x80 ;1 [09]
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282 | in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7
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283 | andi x2, USBMASK ;1 [01]
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284 | breq se0 ;1 [02] SE0 check for stuffed bit 7
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285 | ori shift, 0x80 ;1 [03]
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286 | rjmp didUnstuff7 ;2 [04]
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287 |
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288 | macro POP_STANDARD ; 16 cycles
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289 | pop x4
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290 | pop cnt
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291 | pop bitcnt
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292 | pop x3
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293 | pop x2
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294 | pop x1
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295 | pop shift
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296 | pop YH
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297 | endm
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298 | macro POP_RETI ; 5 cycles
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299 | pop YL
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300 | out SREG, YL
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301 | pop YL
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302 | endm
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303 |
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304 | #include "asmcommon.inc"
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305 |
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306 | ;---------------------------------------------------------------------------
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307 | ; USB spec says:
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308 | ; idle = J
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309 | ; J = (D+ = 0), (D- = 1)
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310 | ; K = (D+ = 1), (D- = 0)
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311 | ; Spec allows 7.5 bit times from EOP to SOP for replies
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312 | ;---------------------------------------------------------------------------
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313 | bitstuffN: ;- [04]
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314 | eor x1, x4 ;1 [05]
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315 | clr x2 ;1 [06]
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316 | nop ;1 [07]
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317 | rjmp didStuffN ;1 [08]
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318 | ;---------------------------------------------------------------------------
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319 | bitstuff6: ;- [04]
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320 | eor x1, x4 ;1 [05]
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321 | clr x2 ;1 [06]
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322 | rjmp didStuff6 ;1 [07]
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323 | ;---------------------------------------------------------------------------
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324 | bitstuff7: ;- [02]
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325 | eor x1, x4 ;1 [03]
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326 | clr x2 ;1 [06]
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327 | nop ;1 [05]
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328 | rjmp didStuff7 ;1 [06]
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329 | ;---------------------------------------------------------------------------
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330 | sendNakAndReti: ;- [-19]
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331 | ldi x3, USBPID_NAK ;1 [-18]
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332 | rjmp sendX3AndReti ;1 [-17]
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333 | ;---------------------------------------------------------------------------
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334 | sendAckAndReti: ;- [-17]
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335 | ldi cnt, USBPID_ACK ;1 [-16]
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336 | sendCntAndReti: ;- [-16]
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337 | mov x3, cnt ;1 [-15]
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338 | sendX3AndReti: ;- [-15]
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339 | ldi YL, 20 ;1 [-14] x3==r20 address is 20
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340 | ldi YH, 0 ;1 [-13]
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341 | ldi cnt, 2 ;1 [-12]
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342 | ; rjmp usbSendAndReti fallthrough
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343 | ;---------------------------------------------------------------------------
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344 | ;usbSend:
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345 | ;pointer to data in 'Y'
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346 | ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
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347 | ;uses: x1...x4, btcnt, shift, cnt, Y
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348 | ;Numbers in brackets are time since first bit of sync pattern is sent
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349 | ;We need not to match the transfer rate exactly because the spec demands
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350 | ;only 1.5% precision anyway.
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351 | usbSendAndReti: ;- [-13] 13 cycles until SOP
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352 | in x2, USBDDR ;1 [-12]
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353 | ori x2, USBMASK ;1 [-11]
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354 | sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups)
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355 | in x1, USBOUT ;1 [-08] port mirror for tx loop
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356 | out USBDDR, x2 ;1 [-07] <- acquire bus
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357 | ; need not init x2 (bitstuff history) because sync starts with 0
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358 | ldi x4, USBMASK ;1 [-06] exor mask
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359 | ldi shift, 0x80 ;1 [-05] sync byte is first byte sent
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360 | ldi bitcnt, 6 ;1 [-04]
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361 | txBitLoop: ;- [-04] [06]
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362 | sbrs shift, 0 ;1 [-03] [07]
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363 | eor x1, x4 ;1 [-02] [08]
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364 | ror shift ;1 [-01] [09]
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365 | didStuffN: ;- [09]
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366 | out USBOUT, x1 ;1 [00] [10] <-- out N
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367 | ror x2 ;1 [01]
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368 | cpi x2, 0xfc ;1 [02]
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369 | brcc bitstuffN ;1 [03]
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370 | dec bitcnt ;1 [04]
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371 | brne txBitLoop ;1 [05]
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372 | sbrs shift, 0 ;1 [06]
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373 | eor x1, x4 ;1 [07]
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374 | ror shift ;1 [08]
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375 | didStuff6: ;- [08]
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376 | nop ;1 [09]
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377 | out USBOUT, x1 ;1 [00] [10] <-- out 6
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378 | ror x2 ;1 [01]
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379 | cpi x2, 0xfc ;1 [02]
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380 | brcc bitstuff6 ;1 [03]
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381 | sbrs shift, 0 ;1 [04]
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382 | eor x1, x4 ;1 [05]
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383 | ror shift ;1 [06]
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384 | ror x2 ;1 [07]
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385 | didStuff7: ;- [07]
|
---|
386 | ldi bitcnt, 6 ;1 [08]
|
---|
387 | cpi x2, 0xfc ;1 [09]
|
---|
388 | out USBOUT, x1 ;1 [00] [10] <-- out 7
|
---|
389 | brcc bitstuff7 ;1 [01]
|
---|
390 | ld shift, y+ ;2 [02+03]
|
---|
391 | dec cnt ;1 [04]
|
---|
392 | brne txBitLoop ;1 [05]
|
---|
393 | makeSE0:
|
---|
394 | cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles]
|
---|
395 | lds x2, usbNewDeviceAddr;2 [07+08]
|
---|
396 | lsl x2 ;1 [09] we compare with left shifted address
|
---|
397 | ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
|
---|
398 | ;set address only after data packet was sent, not after handshake
|
---|
399 | out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle
|
---|
400 | subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3
|
---|
401 | sbci YH, 0 ;1 [02]
|
---|
402 | breq skipAddrAssign ;1 [03]
|
---|
403 | sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer
|
---|
404 | ;----------------------------------------------------------------------------
|
---|
405 | ;end of usbDeviceAddress transfer
|
---|
406 | skipAddrAssign: ;- [03/04]
|
---|
407 | ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [05] int0 occurred during TX -- clear pending flag
|
---|
408 | USB_STORE_PENDING(x2) ;1 [06]
|
---|
409 | ori x1, USBIDLE ;1 [07]
|
---|
410 | in x2, USBDDR ;1 [08]
|
---|
411 | cbr x2, USBMASK ;1 [09] set both pins to input
|
---|
412 | mov x3, x1 ;1 [10]
|
---|
413 | cbr x3, USBMASK ;1 [11] configure no pullup on both pins
|
---|
414 | ldi x4, 3 ;1 [12]
|
---|
415 | se0Delay: ;- [12] [15]
|
---|
416 | dec x4 ;1 [13] [16]
|
---|
417 | brne se0Delay ;1 [14] [17]
|
---|
418 | nop2 ;2 [18+19]
|
---|
419 | out USBOUT, x1 ;1 [20] <--out J (idle) -- end of SE0 (EOP sig.)
|
---|
420 | out USBDDR, x2 ;1 [21] <--release bus now
|
---|
421 | out USBOUT, x3 ;1 [22] <--ensure no pull-up resistors are active
|
---|
422 | rjmp doReturn ;1 [23]
|
---|
423 | ;---------------------------------------------------------------------------
|
---|