[1dc9759] | 1 | ; ---------------------------------------------------------------
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| 2 | ; Copyright 2010, Adrien Destugues <pulkomandy@pulkomandy.ath.cx>
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| 3 | ; Distributed under the terms of the MIT Licence
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[53d1ddc] | 4 | .INCLUDE "2313def.inc"
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[1dc9759] | 5 |
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| 6 | ; Firmware for µSerial expansion board
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| 7 |
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[53d1ddc] | 8 | .EQU ALL_OUT = 255
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| 9 | .EQU ALL_IN = 0
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| 10 |
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| 11 | .EQU DATADIR = DDRB
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| 12 | .EQU DATAOUT = PORTB
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| 13 | .EQU DATAIN = PINB
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| 14 |
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| 15 | .EQU CTRLIN = PIND
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| 16 | .EQU A0 = PIND4
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| 17 |
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| 18 | .EQU curregbak = SRAM_START
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| 19 |
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| 20 | .CSEG
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[1dc9759] | 21 | ; Vectors
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| 22 | ; reset
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[53d1ddc] | 23 | RJMP init
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[1dc9759] | 24 | ; int0
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| 25 | RJMP cpc_write
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| 26 | ; int1
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| 27 | RJMP cpc_read
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| 28 | ; ...
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| 29 |
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| 30 | ; Interrupt vectors for external INT pins (read and write).
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| 31 | ; we have to react very quick.
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| 32 | ; A read operation for the CPC lasts 3 clock cycles at 4MHz, that's 15
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| 33 | ; AVR cycles. But the interrupt latency is as follow :
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| 34 | ; Lowlevel detection ; 2 cycles
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| 35 | ; End of running instruction ; up to 2 cycles
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| 36 | ; Save PC ; 4 cycles
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| 37 | ;Vector RJMP ; 2 cycles
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| 38 | ; TOTAL => 10 cycles
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| 39 |
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| 40 | ; --- READ INTERRUPT ---
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[53d1ddc] | 41 | cpc_read:
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[1dc9759] | 42 | ; That means we only have 5 cycles left to output the value on the BUS!
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| 43 | ; We have no time to do anything, so we assume that X is already pointing at
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| 44 | ; the right place and we just OUT it to the data port. We have no time for
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| 45 | ; PUSHing and loading it, anyway.
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| 46 |
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| 47 | ; Note you can read from either port and get the same result. Two reasons to
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| 48 | ; that : you can already access all the registers and part of the SRAM,
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| 49 | ; and there's no time to do something more clever.
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| 50 |
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| 51 | ; There is no time to push/pop regs, so we just use X as is. R27 is part of X.
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| 52 |
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| 53 | ; We assume X (R26:R27) points to the current reg
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| 54 | ; So we can load it and react fast enough to the interrupt
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[53d1ddc] | 55 | LDI R16,ALL_OUT ; 1 ; peut être économisé si on sacrifie un reg
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[1dc9759] | 56 | OUT DATADIR,R0 ; 1
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[53d1ddc] | 57 | LD R27,X ; 2 cycles ; peut être économisé si un reg. contient
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[1dc9759] | 58 | ; déjà la valeur à envoyer
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| 59 | ; (mais qui l'update ?)
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[53d1ddc] | 60 | OUT DATAOUT, R27 ; 1 cycle
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[1dc9759] | 61 |
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| 62 | ; Here data is sent, the CPC read operation is handled.
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| 63 | ; We now wait for the end of the read cycle.
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| 64 | ; This is not the end of the time-constrained nightmare, however :
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| 65 | ; In the worst case, the CPC can do another OUT or IN right after,
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| 66 | ; so we don't have an infinite number of cycles to handle the interrupt.
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| 67 | ; it is much more relaxed, as we have 12 CPC cycles = 60 AVR cycles free.
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| 68 |
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| 69 | ; Restore R27
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[53d1ddc] | 70 | LDI R27,curregbak
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| 71 | LD R27,X
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[1dc9759] | 72 |
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| 73 | ; release the bus
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[53d1ddc] | 74 | LDI R16,ALL_IN
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| 75 | OUT DATADIR, R16
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[1dc9759] | 76 |
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| 77 | ; Restore R27 to selected reg. (we erased it to do the OUT)
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| 78 | RETI
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| 79 |
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[53d1ddc] | 80 |
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[1dc9759] | 81 | ; --- WRITE INTERRUPT ---
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[53d1ddc] | 82 | cpc_write:
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[1dc9759] | 83 | ; The timing is a bit less constraining here.
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| 84 | PUSH R0
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[53d1ddc] | 85 | IN R0,DATAIN
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[1dc9759] | 86 | ; we also need to know A0 state...
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[53d1ddc] | 87 | SBIS CTRLIN,A0
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[1dc9759] | 88 | ; This was actually a reg select operation!
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| 89 | ; Jump to the proper code
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| 90 | RJMP regSel
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| 91 | ; We have read the CPC data. End of the heavy-constraint area
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| 92 |
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| 93 | ; Register write
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| 94 | ST X,R0 ; Normal register write
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| 95 | RJMP intEnd
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| 96 |
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[53d1ddc] | 97 | regSel:
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| 98 | LDI R27,curregbak
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| 99 | ST X,R0
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[1dc9759] | 100 | MOV R27,R0
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| 101 |
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[53d1ddc] | 102 | intEnd:
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[1dc9759] | 103 | POP R0
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| 104 | RETI
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| 105 |
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| 106 |
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| 107 | ; --- RESET VECTOR ---
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| 108 | ; Here we perform the hardware initialization.
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| 109 | ; At a bare minimum :
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| 110 | ; * Set up the INT0 and INT1 so the CPC can do the rest of the setup itself
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[53d1ddc] | 111 | init:
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| 112 | RJMP init
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